dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 59
dsp56800
Manufacturer Part Number
dsp56800
Description
16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56800.pdf
(448 pages)
- Current page: 59 of 448
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The representation of numbers allowed on the DSP56800 architecture are as follows:
The different representations not only affect the arithmetic operations, but also the condition code
generation. These numbers can be represented as decimal, hexadecimal, or binary numbers.
To maintain alignments of the binary point when a word operand is written to an accumulator A or B, the
operand is written to the most significant accumulator register (A1 and B1) and its most significant bit is
automatically sign extended through the accumulator extension register. The least significant accumulator
register is automatically cleared.
Some of the advantages of fractional data representation are as follows:
Freescale Semiconductor
16-Bit Word Operand
32-Bit Long Word Operand
32-Bit Long Word Operand
•
•
•
•
•
•
16-Bit Word Operand
36-Bit Accumulator
36-Bit Accumulator
X0,Y0,Y1,A1,B1,
16-Bit Memory
X0,Y0,Y1,A1,B1,
16-Bit Memory
Two’s-complement values
Fractional or integer values
Signed or unsigned values
Word (16-bit), long word (32-bit), or accumulator (36-bit)
The MSP (left half) has the same format as the input data.
The LSP (right half) can be rounded into the MSP without shifting or updating the exponent.
Y = Y1:Y0
in A1,B1
A,B
A,B
Figure 3-8. Bit Weightings and Operand Alignments
-2
-2
4
35
Fractional Two’s-Complement Representations
-2
-2
2
-2
2
Integer Two’s-Complement Representations
0
31
0
0
31
Data Arithmetic Logic Unit
Fractional and Integer Data ALU Arithmetic
2
2
2
2
2
-15
-15
-15
16
16
2
2
-2
2
2
-16
-16
15
15
15
2
14
AA0041
2
2
-31
-31
2
2
2
0
0
0
3-15
.
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