dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 229

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

9.3.2.1
The command, status and control portion of the OnCE port module handles the processing of emulation
and debugging commands from a host development system. Communications with a host system are
provided by the JTAG port module, and are passed transparently through to this logic, which is responsible
for coordinating all emulation and debugging activity.
As previously noted, all emulation and debug processing takes place independently of the main DSP56800
processor core. This allows for instructions to be executed in debug mode at full speed, without any
overhead introduced by the debugging logic.
9.3.2.2
The OnCE port module includes address-comparison hardware for setting breakpoints on program or data
memory accesses. This allows breakpoints to be set on program FLASH as well as program RAM
locations. Breakpoints can be programmed for reads, writes, program fetches, or memory accesses.
Breakpoints are also possible during on-chip peripheral register accesses, since these are implemented as
memory-mapped registers in the X data space.
Full-speed instruction stepping capability is also provided. Up to 256 instructions can be executed at full
speed before the processor core is halted and the debug processing state is re-entered. This allows the user
to single step through a program or execute whole functions at a time.
9.3.2.3
To resume normal chip activity when the chip is returning from the debug mode, the previous chip pipeline
state must be reconstructed. The OnCE port module provides logic to correctly save and restore the
pipeline state when entering and exiting debug mode. Pipeline saves and restores operate transparently to
the user, although the pipeline state may be examined while in debug mode if desired.
9.3.2.4
To ease debugging activity and to help keep track of program flow, a read-only FIFO buffer is provided
that tracks the execution history of an application. It stores the address of the instruction currently being
executed by the processor core, as well as the addresses of the last five execution flow instructions.
The FIFO history buffer is intended to provide a snapshot of the recent execution history of the processor
core. To give a larger picture of instruction flow, not all instructions are recorded in the buffer. Only the
addresses of the following execution flow instructions are stored:
Sequential program flow can be assumed between recorded instructions, so it is possible for the user to
reconstruct the program flow extending back through quite a large number of instructions. To complete the
execution history, the first location of the FIFO always holds the address of the last executed instruction,
regardless of whether or not it caused a change of program flow.
Freescale Semiconductor
Command, Status, and Control
Breakpoint and Trace
Pipeline Save and Restore
FIFO History Buffer
BRA
JSR
Jcc (with condition true)
JTAG and On-Chip Emulation (OnCE™)
JMP
Bcc (with condition true)
OnCE Port
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