dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 183

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

7.5
The STOP instruction brings the processor into the stop processing state, which is the lowest
power-consumption state. In the stop state the clock oscillator is gated off, whereas in the wait state the
clock oscillator remains active. The chip clears all peripheral interrupts and external interrupts (IRQA,
IRQB, and NMI) when it enters the stop state. Stack errors that were pending remain pending. The priority
levels of the peripherals remain as they were before the STOP instruction was executed. The on-chip
peripherals are held in their respective, individual reset states while the processor is in the stop state.
The stop processing state halts all activity in the processor until one of the following actions occurs:
Any of these actions will activate the oscillator, and after a clock stabilization delay, clocks to the
processor and peripherals will be re-enabled. The clock-stabilization delay period is equal to either 16 (T)
cycles or 131,072 T cycles as determined by the stop delay (SD) bit in the OMR. One T cycle is equal to
one half of a clock cycle. For example, according to Table 6-34 on page 6-28, one NOP instruction
executes in 2 clock cycles; therefore, one NOP instruction executes in 4T cycles, i.e., 1 instruction cycle
equals 2 clock cycles and is equal to 4T cycles.
The stop sequence is composed of eight instruction cycles called stop cycles. They are differentiated from
normal instruction cycles because the fourth cycle is stretched for an indeterminate period of time while
the four-phase clock is turned off.
As shown in Figure 7-10, the STOP instruction is fetched in stop cycle 1, decoded in stop cycle 2 (which is
where it is first recognized as a stop command), and executed in stop cycle 3. The next instruction (n4) is
fetched during stop cycle 2 but is not decoded in stop cycle 3 because, by that time, the STOP instruction
prevents the decode. The processor stops the clock and enters the stop mode. The processor will stay in the
stop mode until it is restarted.
Figure 7-11 shows the system being restarted through asserting the IRQA signal. If the exit from the stop
state was caused by a low level on the IRQA pin, then the processor will service the highest priority
pending interrupt. If no interrupt is pending, then the processor resumes at the instruction following the
STOP instruction that brought the processor into the stop state.
Freescale Semiconductor
Fetch
Decode
Execute
Stop Cycle Count
IRQA
IRQA = Interrupt Request A Signal
n = Normal Instruction Word
STOP = Interrupt Instruction Word
•
•
•
A low level is applied to the IRQA pin
A low level is applied to the RESET pin
An on-chip timer reaches zero
Stop Processing State
n3
n2
n1
1
STOP
n4
n2
2
STOP
—
—
Figure 7-10. STOP Instruction Sequence
3
Clock Stopped
Interrupts and the Processing States
STOP
—
—
4
STOP
—
—
5
STOP
—
—
6
131,072 T or 16 T
Cycle Count Started
Resume Stop Cycle Count 6,
Interrupts Enabled
7
8
9
10
Stop Processing State
11
12
AA0076
(13)
n4
7-19