dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 122

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Program Controller
5.1.7
The hardware stack (HWS) is a 2-deep, 16-bit wide, last-in-first-out (LIFO) stack. It is used for supporting
hardware DO looping; the software stack is used for storing return addresses and the SR for subroutines
and interrupts.
When a DO instruction is executed, the 16-bit address of the first instruction in the DO loop is pushed onto
the hardware stack, the value of the LF bit is copied into the NL bit, and the LF bit is set. Each ENDDO
instruction or natural end-of-loop will pop and discard the 16-bit address stored in the top location of the
hardware stack, copy the NL bit into the LF bit, and clear the NL bit. One hardware stack location is used
for each nested DO loop, and the REP instruction does not use the hardware stack. Thus, a two-deep
hardware stack allows for a maximum of two nested DO loops and a nested REP loop within a program.
Note that this includes any looping that may occur due to a DO loop in an interrupt service routine.
When a write to the hardware stack would cause the stack limit to be exceeded, the write does not take
place, and a non-maskable hardware-stack-overflow interrupt occurs. There is no interrupt on hardware
stack underflow.
5.1.8
The status register (SR) is a 16-bit register consisting of an 8-bit mode register (MR) and an 8-bit condition
code register (CCR). The MR register is the high-order 8 bits of the SR; the CCR register is the low-order
8 bits.
The mode register is a special-purpose register that defines the operating state of the DSC core. It is
conveniently located within the SR so that is it stacked correctly on an interrupt. This allows an interrupt
service routine to set up the operating state of the DSC core differently.
The mode register bits are affected by processor reset, exception processing, DO, ENDDO, any type of
jump or branch, RTI, RTS, and SWI instructions, and instructions that directly reference the MR register.
During processor reset, the interrupt mask bits of the mode register will be set, and the LF bit will be
cleared.
The condition code register is a special-purpose control register that defines the current status of the
processor at any given time. Its bits are set as a result of status detected after certain instructions are
executed. The CCR bits are affected by data ALU operations, bit-field manipulation instructions, the
TSTW instruction, parallel move operations, and instructions that directly reference the CCR register. In
addition, the computation of the C, V, N, and Z condition code bits are affected by the OMR’s CC bit,
which specifies whether condition codes are generated using the information in the extension register. The
CCR bits are not affected by data transfers over the CGDB unless data limiting occurs when reading the A
or B accumulators. During processor reset, all CCR bits are cleared. The standard definitions of the CCR
bits are given in the following subsections, and more information about condition code bits is found in
Section 3.6, “Condition Code Generation,” on page 3-33. Refer to Appendix A, “Instruction Set Details,“
for computation rules.
The SR register is stacked on the software stack when a JSR is executed or when an interrupt occurs. The
SR register is restored from the stack upon completion of an interrupt service routine by the
return-from-interrupt instruction (RTI). The program extension bits in the SR are restored from the stack
by the return-from-subroutine (RTS) instruction — all other SR bits are unaffected.
The SR format is shown in Figure 5-4 on page 5-7 and is also described in the following subsections.
5-6
Hardware Stack
Status Register
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