dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 293

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

CMP
Operation:
D - S
D - S
Description: Subtract the first operand from the second operand and update the CCR without storing the result. If
Usage:
Note:
Example:
Explanation of Example:
Freescale Semiconductor
Before Execution
A2
SR
Y0
0
(single parallel move)
the second operand is a 36-bit accumulator, 16-bit source registers are first sign extended internally
and concatenated with 16 zero bits to form a 36-bit operand. When the second operand is X0, Y0, or
Y1, 16-bit subtraction is performed. In this case, if the first operand is one of the four accumulators;
the FF1 portion (properly sign extended) is used in the 16-bit subtraction (the FF2 and FF0 portions
are ignored).
This instruction can be used for both integer and fractional two’s-complement data.
When a word is specified as the source, it is sign extended and zero filled to form a valid 36-bit oper-
and. In order for C to be set correctly as a result of the subtraction, the destination must be properly
sign extended. The destination can be improperly sign extended by writing A1 or B1 explicitly prior
to executing the compare, so that A2 or B2, respectively, may not represent the correct sign extension.
This note particularly applies to the case in which the source is extended to compare 16-bit operands,
such as X0 with A1.
CMP
Prior to execution, the 36-bit A accumulator contains the value $0:0020:0000, and the 16-bit Y0 reg-
ister contains the value $0024. Execution of the CMP Y0,A instruction automatically appends the
16-bit value in the Y0 register with 16 LS zeros, sign extends the resulting 32-bit long word to 36 bits,
subtracts the result from the 36-bit A accumulator, and updates the CCR (leaving the A accumulator
unchanged).
0020
0024
0300
A1
Y0,A
0000
A0
Instruction Set Details
X0,X:(R1)+N
Compare
Assembler Syntax:
CMP
CMP
After Execution
A2
SR
Y0
0
S,D
S,D
; compare Y0 and A, save X0,
;
0020
0024
0319
A1
update R1
(single parallel move)
0000
A0
CMP
A-63