dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 270

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

ASLL
Operation:
S1 << S2 → D
Description: Arithmetically shifts the source operand S1 to the left by the value contained in the lowest 4 bits of S2,
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
Timing:
Memory:
A-40
Operation
ASLL
Before Execution
A2
0
and stores the result in the destination (D) with zeros shifted into the LSB. For 36-bit destinations, only
the MSP is shifted and the LSP is cleared, with sign extension from bit 31 (the FF2 portion is ignored).
The result is not affected by the state of the saturation bit (SA).
ASLL
Prior to execution, the Y1 register contains the value to be shifted ($AAAA) and the X0 register con-
tains the amount by which to shift ($0004). The contents of the destination register are not important
prior to execution because they have no effect on the calculated value. The ASLL instruction arithmet-
ically shifts the value $AAAA four bits to the left and places the result in the destination register A.
Since the destination is an accumulator, the extension word (A2) is filled with sign extension, and the
LSP (A0) is set to zero.
Note:
2 oscillator clock cycles
1 program word
LF
15
3456
A1
14
*
N
Z
If the CC bit is set, N is undefined and Z is set if the LSBs 31–0 are zero.
13
*
Y1,X0,FDD
Y0,X0,FDD
Y1,Y0,FDD
Y0,Y0,FDD
A1,Y0,FDD
B1,Y1,FDD
Y1
X0
Operands
— Set if MSB of result is set
— Set if result equals zero
Y1,X0,A
Multi-Bit Arithmetic Left Shift
12
*
MR
11
AAAA
*
3456
0004
A0
DSP56800 Family Manual
10
*
I1
9
C
2
Assembler Syntax:
ASLL
I0
8
W
1
SZ
7
After Execution
Arithmetic shift left of the first operand by value speci-
fied in four LSBs of the second operand; places result in
FDD
A2
6
L
F
5
E
S1,S2,D
AAA0
U
4
CCR
A1
N
3
Y1
X0
Z
Comments
2
V
1
Freescale Semiconductor
AAAA
0000
0004
A0
C
0
ASLL