dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 268

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

ASL
Operation:
(see figure)
:
Description: Arithmetically shift the destination operand (D) 1 bit to the left, and store the result in the destination.
Implementation Note:
Example:
Explanation of Example:
Condition Codes Affected:
A-38
Before Execution
A2
SR
A
The MSB of the destination prior to the execution of the instruction is shifted into C, and a zero is shift-
ed into the LSB of the destination. A duplicate destination is not allowed when ASL is used in con-
junction with a parallel read.
When a 16-bit register is specified as the operand for ASL, this instruction is actually assembled as an
LSL with the same register argument.
ASL
Prior to execution, the 36-bit A accumulator contains the value $A:0123:0123. Execution of the
ASL A instruction shifts the 36-bit value in the A accumulator 1 bit to the left and stores the result
back in the A accumulator. C is set by the operation because bit 35 of A was set prior to the execution
of the instruction. The V bit of CCR (bit 1) is also set because bit 35 of A has changed during the ex-
ecution of the instruction. The U bit of CCR (bit 4) is set because the result is not normalized, the E bit
of CCR (bit 5) is set because the signed integer portion of the result is in use, and the L bit of CCR (bit
6) is set because an overflow has occurred.
See Section 3.6.5, “16-Bit Destinations,” Section 3.6.2, “36-Bit Destinations — CC Bit Set,” and
Section 3.6.4, “20-Bit Destinations — CC Bit Set.”
C
LF
15
0123
0300
14
A1
*
SZ — Set according to the standard definition of the SZ bit (parallel move)
L
E
U
N
Z
V
C
D2
13
*
— Set if limiting (parallel move) or overflow has occurred in result
— Set if the extension portion of accumulator result is in use
— Set according to the standard definition of the U bit
— Set if MSB of result is set
— Set if result equals zero
— Set if bit 35 of accumulator result is changed due to left shift
— Set if bit 35 of accumulator was set prior to the execution of the instruction
A
12
*
MR
11
*
D1
0123
Arithmetic Shift Left
A0
DSP56800 Family Manual
10
X:(R3)+N,Y0
*
I1
9
Assembler Syntax:
ASL
ASL
I0
8
D0
SZ
7
After Execution
L
6
A2
SR
4
E
5
D
D
; multiply A by 2,
;
U
4
CCR
0246
0373
0
A1
update R3,Y0
N
3
Z
2
(single parallel move)
V
(single parallel move)
1
Freescale Semiconductor
0246
C
0
A0
ASL