dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 253

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Problem
Calculate the number of DSP56800 instruction program words and the number of oscillator clock cycles
required for the following instruction:
Where the following conditions are true:
2. Evaluate the “mv” term using Table A-12 on page A-19.
3. Evaluate the “axx” term using Table A-20 on page A-22.
4. Compute the final results.
•
•
The parallel move portion of the MACR instruction consists of an XX memory read.
According to Table A-12 on page A-19, the parallel move portion of the instruction will
require mv = axx additional oscillator clock cycles. The term “axx” represents the number
of additional oscillator clock cycles (if any) that are required to access two operands in the
X memory.
The parallel move portion of the MACR instruction consists of an XX Memory Read.
According to Table A-20 on page A-22, the term “axx” depends upon where the
referenced X memory locations are located in the DSP56800 memory space. External X
memory accesses may require additional oscillator clock cycles depending on the memory
device’s speed. Here we assume external X memory accesses require wx = 0 wait state or
additional oscillator clock cycle. For this example, the second X memory reference is
assumed to be an internal reference, while the first X memory reference is assumed to be
an external reference. Thus, according to Table A-20 on page A-22, the XX memory
reference in the parallel move portion of the MACR instruction will require axx = wx = 0
additional oscillator clock cycle.
Thus, based upon the assumptions given for Table A-11 on page A-18, the instruction
MACR
will require 1 instruction program word and will execute in
(2 + mv) = (2 + axx) = (2 + wx) = (2 + 0) = 2 oscillator clock cycles.
JEQ
OMR = $02 (normal expanded memory map).
External P memory accesses require four wait states (assume external memory access requires 4
wait states in this example).
Example A-1. Arithmetic Instruction with Two Parallel Reads (Continued)
If a similar calculation were made for a MOVEC, MOVEM, or one of the
bit-field manipulation instructions (BFCHG, BFCLR, BFSET, BFTSTH
or BFTSTL), using Table A-12 on page A-19 would no longer be
appropriate. The user would refer to Table A-13 on page A-20,
Table A-14 on page A-20, or Table A-15 on page A-20, respectively.
$2000
X0,Y0,A
X:(R0)+,Y0
Example A-2. Jump Instruction
Instruction Set Details
X:(R3)+,X
NOTE:
A-23