dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 74

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Data Arithmetic Logic Unit
Also, the MAC Output Limiter only affects operations performed in the data ALU. It has no effect on
instructions executed in other blocks of the core, such as the following:
3.5
The DSP56800 provides three instructions that can perform rounding — RND, MACR, and MPYR. The
RND instruction simply rounds a value in the accumulator register specified by the instruction, whereas
the MPYR or MACR instructions round the result calculated by the instruction in the MAC array. Each
rounding instruction rounds the result to a single-precision value so the value can be stored in memory or
in a 16-bit register. In addition, for instructions where the destination is one of the two accumulators, the
LSP of the destination accumulator (A0 or B0) is set to $0000.
The DSC core implements two types of rounding: convergent rounding and two’s-complement rounding.
For the DSP56800, the rounding point is between bits 16 and 15 of a 36-bit value; for the A accumulator, it
is between the A1 register’s LSB and the A0 register’s MSB. The usual rounding method rounds up any
value above one-half (that is, LSP > $8000) and rounds down any value below one-half (that is, LSP <
$8000). The question arises as to which way the number one-half (LSP = $8000) should be rounded. If it is
always rounded one way, the results will eventually be biased in that direction. Convergent rounding
solves the problem by rounding down if the number is even (bit 16 equals zero) and rounding up if the
number is odd (bit 16 equals one), whereas two’s-complement rounding always rounds this number up.
The type of rounding is selected by the rounding bit (R) of the operating mode register (OMR) in the
program controller.
3.5.1
This is the default rounding mode. This rounding is also called “round to nearest even number.” For most
values, this mode rounds identically to two’s-complement rounding; it only differs for the case where the
least significant 16 bits is exactly $8000. For this case, convergent rounding prevents any introduction of a
bias by rounding down if the number is even (bit 16 equals zero) and rounding up if the rounding is odd
(bit 16 equals one). Figure 3-15 on page 3-31 shows the four possible cases for rounding a number in the A
or B accumulator.
3-30
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Bit Manipulation Instructions (Table 6-30 and Table 6-31 on page 6-26)
Move instructions (Table 6-18 through Table 6-21)
Looping instructions (Table 6-33 on page 6-27)
Change of flow instructions (Table 6-32 on page 6-27)
Control instructions (Table 6-34 on page 6-28)
Rounding
Convergent Rounding
The SA bit affects the TFR instruction when it is set, optionally limiting
data as it is transferred from one accumulator to another.
DSP56800 Family Manual
NOTE:
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