dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 255

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Problem
Calculate the number of DSP56800 instruction program words and the number of oscillator clock cycles
required for the following instruction:
Where the following conditions are true:
Solution
To determine the number of instruction program words and the number of oscillator clock cycles required
for the given instruction, the user should perform the following steps:
•
•
•
1. Look up the number of instruction program words and the number of oscillator clock cycles
2. Evaluate the “rx” term using Table A-17 on page A-21.
3. Evaluate the “ap” term using Table A-20 on page A-22.
4. Compute the final results.
RTS
OMR = $02 (normal expanded memory map).
External P memory accesses require four wait states.
Return Address (on the stack) = $0100 (internal P memory).
required for the opcode-operand portion of the instruction in Table A-11 on page A-18.
According to Table A-11 on page A-18, the RTS instruction will require one instruction
program word and will execute in (10 + rx) oscillator clock cycles. The term “rx” represents
the number of additional oscillator clock cycles (if any) required for an RTS instruction.
According to Table A-17 on page A-21, the RTS instruction will require rx = 2 * ap + 2 *
ax additional oscillator clock cycles. In this case “ax = 0” because the instruction accesses
the stack on internal memory. The term “ap” represents the number of additional oscillator
clock cycles (if any) that are required to access a P memory operand. The term “(2 * ap)”
represents the two program memory instruction fetches executed at the end of an RTS
instruction to refill the instruction pipeline.
According to Table A-20 on page A-22, the term “ap” depends upon where the referenced
P memory location is located in the 16-bit DSC memory space. External memory accesses
may require additional oscillator clock cycles, according to the memory device’s speed.
Here we assume that external P memory accesses require wp = 4 wait states or additional
oscillator clock cycles. For this example the P memory reference is assumed to be an
internal reference. This means that the return address ($0100) pulled from the system
stack by the RTS instruction is in internal P memory. Thus, according to Table A-20 on
page A-22, the RTS instruction will use the value ap = 0 additional oscillator clock cycles.
Thus, based upon the assumptions given for Table A-11 on page A-18, the instruction
RTS
will require one instruction program word and will execute in (10 + rx) = (10 + (2 * ap) +
(2 * ax)) = (10 + (2 * 0) + (2 * 0)) = 10 oscillator clock cycles.
Example A-3. RTS Instruction
Instruction Set Details
A-25