dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 320

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

LSLL
Operation:
S1 << S2 → D
Description: Logically shift the first 16-bit source operand S1 to the left by the value contained in the lowest 4 bits
Implementation Note:
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
Timing:
Memory:
A-90
Operation
LSLL
Before Execution
of the second source operand S2 and store the result in the destination register (D). The destination
must always be a 16-bit register. The LSLL instruction operates identically to an multi bit arithmetic
left shift.
This instruction is actually implemented by the assembler using the ASLL instruction. It will disas-
semble as ASLL.
LSLL
Prior to execution, the Y1 register contains the value to be shifted ($AAAA) and the X0 register con-
tains the amount to shift by ($0004). The contents of the destination register are not important prior to
execution because they have no effect on the calculated value. The LSLL instruction logically shifts
the value $AAAA four bits to the left and places the result in the destination register Y1.
2 oscillator clock cycles
1 program word
LF
15
14
*
N
Z
13
*
Y1,X0,DD
Y0,X0,DD
Y1,Y0,DD
Y0,Y0,DD
A1,Y0,DD
Operands
B1,Y1,DD
Y1
X0
— Set if bit 15 of result is set
— Set if the result in D is zero
Y1,X0,Y1
12
*
MR
Multi-Bit Logical Left Shift
11
*
AAAA
0004
DSP56800 Family Manual
10
*
I1
9
C
2
Assembler Syntax:
LSLL
I0
8
W
1
S
7
; left shift of 16-bit Y1 by X0
After Execution
Logical shift left of the first operand by value specified in
four LSBs of the second operand; places result in DD.
Use ASLL when left shifting is desired on one of the two
accumulators.
ALIAS, refer to Section 6.5.2, “LSLL Alias.”
Implemented as: ASLL <operands>
6
L
5
E
S1,S2,D
U
4
CCR
N
3
Y1
X0
Z
Comments
2
V
1
Freescale Semiconductor
AAA0
0004
C
0
LSLL