dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 37

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

2.1.1
The data arithmetic logic unit (ALU) performs all of the arithmetic and logical operations on data
operands. It consists of the following:
The data ALU is capable of multiplication, multiply-accumulation (with positive or negative
accumulation), addition, subtraction, shifting, and logical operations in one instruction cycle. Arithmetic
operations are done using two’s-complement fractional or integer arithmetic. Support is also provided for
unsigned and multi-precision arithmetic.
Data ALU source operands may be 16, 32, or 36 bits and may individually originate from input registers,
memory locations, immediate data, or accumulators. ALU results are stored in one of the accumulators. In
addition, some arithmetic instructions store their 16-bit results either in one of the three data ALU input
registers or directly in memory. Arithmetic operations and shifts can have a 16-bit or a 36-bit result.
Logical operations are performed on 16-bit operands and always yield 16-bit results.
Data ALU register values can be transferred (read or write) across the core global data bus (CGDB) as
16-bit operands. The X0 register value can also be written by X memory data bus two (XDB2) as a 16-bit
operand. Refer to Chapter 3, “Data Arithmetic Logic Unit,” for a detailed description of the data ALU.
2.1.2
The address generation unit (AGU) performs all of the effective address calculations and address storage
necessary to address data operands in memory. The AGU operates in parallel with other chip resources to
minimize address-generation overhead. It contains two ALUs, allowing the generation of up to two 16-bit
addresses every instruction cycle: one for either X memory address bus one (XAB1) or program address
bus (PAB) and one for X memory address bus two (XAB2). The ALU can directly address 65,536
locations on the XAB1 or XAB2 and 65,536 locations on the PAB, totaling 131,072 sixteen-bit data words.
It supports a complete set of addressing modes. Its arithmetic unit can perform both linear and modulo
arithmetic.
The AGU contains the following registers:
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Three 16-bit input registers (X0, Y0, and Y1)
Two 36-bit accumulator registers (A and B)
— 16-bit registers (A0 and B0)
— 16-bit registers (A1 and B1)
— 4-bit extension registers (A2 and B2)
An accumulator shifter (AS)
One data limiter
One 16-bit barrel shifter
One parallel (single cycle, non-pipelined) multiply-accumulator (MAC) unit
Four address registers (R0-R3)
A stack pointer register (SP)
An offset register (N)
A modifier register (M01)
A modulo arithmetic unit
An incrementer/decrementer unit
Data Arithmetic Logic Unit (ALU)
Address Generation Unit (AGU)
Core Architecture Overview
Core Block Diagram
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