dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 319

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

LSL
Operation:
(see figure)
Description: Logically shift 16 bits of the destination operand (D) by 1 bit to the left, and store the result in the des-
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
Timing:
Memory:
Freescale Semiconductor
Operation
LSL
Before Execution
B2
SR
6
tination. If the destination is a 36-bit accumulator, the result is stored in the MSP of the accumulator
(FF1 portion), and the remaining portions of the accumulator are not modified. The MSB of the desti-
nation (bit 31 if the destination is a 36-bit accumulator) prior to the execution of the instruction is shift-
ed into C, and zero is shifted into the LSB of D1 (bit 16 if the destination is a 36-bit accumulator). The
result is not affected by the state of the saturation bit (SA).
LSL
Prior to execution, the 36-bit B accumulator contains the value $6:8000:00AA. Execution of the
LSL B instruction shifts the 16-bit value in the B1 register 1 bit to the left and stores the result back
in the B1 register. C is set by the operation because bit 31 of B1 was set prior to the execution of the
instruction. The Z bit of CCR (bit 2) is also set because the result in B1 is zero.
2 oscillator clock cycles
1 program word
LF
15
8000
0300
14
B1
*
N
Z
V
C
13
C
*
Operands
— Set if bit 31 of accumulator result or MSB or register result is set
— Set if the MSP of result or all bits of 16-bit register result are zero
— Always cleared
— Set if bit 31 of accumulator or MSB of register was set prior to the execution of
FDD
B
12
*
MR
the instruction
Unch.
11
*
00AA
D2
B0
Logical Shift Left
10
*
Instruction Set Details
I1
9
C
2
D1
Assembler Syntax:
LSL
I0
8
W
1
SZ
7
; shift 1 bit left
After Execution
1-bit logical shift left of word
6
L
B2
SR
6
Unchanged
5
E
D0
D
U
4
CCR
0000
0305
B1
N
3
Z
Comments
2
0
V
1
00AA
C
0
B0
LSL
A-89