dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 245

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
1. V is set if the MSB of the destination operand (bit 35 for an accumulator or bit 31 for the Y
2. C is set if the MSB of the source operand (bit 35 for an accumulator or bit 31 for the Y
3. C is set if bit 0 of the source operand is set and is cleared otherwise.
4. C is set if all bits specified by the mask are set and is cleared otherwise. Bits that are not set
5. C is set if all bits specified by the mask are cleared and is cleared otherwise. Ignore bits that
6. C is set if the MSB of the result is cleared (bit 35 for an accumulator or bit 31 for the Y
7. For the accumulators, C is set if bit 31 of the source operand is set and is cleared otherwise.
8. For the accumulators, C is set if bit 16 of the source operand is set and is cleared otherwise.
Instruction
TSTW
WAIT
STOP
register) is changed as a result of the left shift; V is cleared otherwise.
register) is set and is cleared otherwise.
in the mask should be ignored. If a bit-field instruction is performed on the status register,
all bits in this register selected by the bit field’s mask can be affected.
are not set in the mask. Note that if a bit-field instruction is performed on the status register,
all bits in this register selected by the bit field’s mask can be affected.
register). The C bit is cleared if the MSB of the result is set.
For the Y1, Y0, and X0 registers, C is set if bit 15 of the source operand is set and is cleared
otherwise.
For the Y1, Y0, and X0 registers, C is set if bit 0 of the source operand is set and is cleared
otherwise.
RND
ROL
ROR
SBC
SUB
REP
RTS
SWI
TFR
TST
RTI
Tcc
SZ
—
—
—
—
—
—
—
—
—
—
*
*
*
*
Table A-9. Condition Code Summary (Continued)
CT
CT
CT
—
—
—
—
—
—
—
—
L
C
T
T
*36
*36
*36
*A
—
—
—
—
—
—
—
—
—
—
E
Restored — (9)
Instruction Set Details
*36
*36
*36
*A
—
—
—
—
—
—
—
—
—
—
U
NOTES:
*36
*16
*16
*36
*36
*36
*A
—
—
—
—
—
—
—
N
*36
*16
*16
*36
*36
*36
*A
—
—
—
—
—
—
—
Z
*36
*36
*A
=0
=0
—
—
—
—
—
—
—
V
0
0
*36
(7)
(8)
*A
—
—
—
—
—
—
—
—
C
0
0
Affects I1, I0 bits in SR
Never overflows
Never overflows
Comments
A-15