dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 39

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

2.1.4
Transfers between internal buses are accomplished in the bus unit. The bus unit is similar to a switch
matrix and can connect any two of the three internal data buses together without introducing delays. This
allows data to be moved from program to data memory, for example. The bus unit is also used to transfer
data to the IP-Bus (or PGDB) on those devices that use it to connect to on-chip peripherals.
The bit-manipulation unit performs bit-field manipulations on X (data) memory words, peripheral
registers, and all registers within the DSP56800 core. It is capable of testing, setting, clearing, or inverting
any bits specified in a 16-bit mask. For branch-on-bit-field instructions, this unit tests bits on the upper or
lower byte of a 16-bit word (that is, the mask can only test up to 8 bits at a time).
Note that when the IP-BUS (or PGDB) interface is used, peripheral registers may be memory mapped into
any data (X) memory address range and are accessed with standard X-memory reads and writes. If the
peripheral registers are mapped to the last 64 locations in X memory, these can be accessed with a special
memory addressing mode (see Section 4.2.4.3, “I/O Short Address (Direct Addressing): <pp>,” on
page 4-23).
2.1.5
The On-Chip Emulation (OnCE) unit allows the user to interact in a debug environment with the
DSP56800 core and its peripherals non-intrusively. Its capabilities include examining registers, on-chip
peripheral registers or memory, setting breakpoints on program or data memory, and stepping or tracing
instructions. It provides simple, inexpensive, and speed-independent access to the internal DSP56800 core
by interacting with a user-interface program running on a host workstation for sophisticated debugging and
economical system development.
Dedicated pins through the JTAG port allow the user access to the DSC in a target system, retaining debug
control without sacrificing other user-accessible on-chip resources. This technique eliminates the costly
cabling and the access to processor pins required by traditional emulator systems. Refer to Chapter 9,
“JTAG and On-Chip Emulation (OnCE™),” for a detailed description of the JTAG/OnCE port. Consult
your development system’s documentation for information on debugging using the JTAG/OnCE port
interface.
2.1.6
Addresses are provided to the internal X data memory on two unidirectional 16-bit buses, X memory
address bus one (XAB1) and X memory address bus two (XAB2). Program memory addresses are
provided on the 16-bit program address bus (PAB). Note that XAB1 can provide addresses for accessing
both internal and external memory, whereas XAB2 can only provide addresses for accessing internal
memory.
2.1.7
Inside the chip, data is transferred using the following:
Freescale Semiconductor
•
•
Bidirectional 16-bit buses:
— Core global data bus (CGDB)
— Program data bus (PDB)
— IB-BUS or Peripheral Global data bus (PGDB) — dependent on chip implementation
One unidirectional 16-bit bus: X memory data bus two (XDB2)
Bus and Bit-Manipulation Unit
On-Chip Emulation (OnCE) Unit
Address Buses
Data Buses
Core Architecture Overview
Core Block Diagram
2-5