dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 201

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

8.4.2
The algorithms in the following code provide fast ways to divide two signed, two’s-complement numbers.
These algorithms are faster because they generate the quotient only; they do not generate a correct
remainder. The algorithms are referred to as four-quadrant division because they allow any combination of
positive or negative operands for the dividend and divisor. One algorithm is presented for the division of
fractional numbers, and a second is presented for the division of integer numbers.
; 4-Quadrant Signed Fractional Division with no Remainder: (B1:B0 / X0)
; Generates signed quotient only, no remainder. Registers used: Y1
;
; Setup
; Division Operation
; Compute Correct Quotient
QDONE:
; 4-Quadrant Signed Integer Division with no Remainder: (B1:B0 / X0)
; Generates signed quotient only, no remainder. Registers used: Y1
;
; Setup
; Division Operation
; Compute Correct Quotient
QDONE:
Freescale Semiconductor
Results: B1 = unknown, B0 = Quotient, X0 (not modified), B (modified)
Results: B1 = unknown, B0 = Quotient, X0 (not modified), B (modified)
MOVE
ABS
TSTW
REP
DIV
EOR
BGE
NEG
ASL
MOVE
ABS
TSTW
REP
DIV
EOR
BGE
NEG
Signed Dividend and Divisor with No Remainder
B,Y1
B
B
#16
X0,B
X0,Y1
QDONE
B
B
B,Y1
B
B
#16
X0,B
X0,Y1
QDONE
B
; Copy dividend to Y1
; Force the dividend positive
; TSTW always clears carry bit and more efficient
;
; Carry bit must be clear for first DIV
; Form positive quotient in B0
; If dividend and divisor both neg or both pos
;
; Else quotient is negative of computed result
; At this point, the correctly signed quotient
;
; End of Algorithm.
; Shift of dividend required for integer division
; Save Sign Bit of dividend (B1) in MSB of Y1
; Force the dividend positive
; TSTW always clears carry bit and more efficient
;
; Carry bit must be clear for first DIV
; Form positive quotient in B0
; If dividend and divisor both neg or both pos
;
; Else quotient is negative of computed result
; At this point, the correctly signed quotient
;
; End of Algorithm.
Software Techniques
than using BFCLR
quotient already has correct sign,
is at B0 but the remainder is not correct.
than using BFCLR
quotient already has correct sign,
is at B0 but the remainder is not correct.
#$0001,SR
#$0001,SR
Division
8-15