dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 324

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

MAC
Operation:
+ D + S1 * S2 → D
Description: Multiply the two signed 16-bit source operands, and add or subtract the 32-bit fractional product to or
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
A-94
D + S1 * S2 → D (single parallel move)
D + S1 * S2 → D (dual parallel read)
Before Execution
A2
0
from the destination (D). Both source operands must be located in the FF1 portion of an accumulator
or in X0, Y0, or Y1. The fractional product is first sign extended before the 36-bit addition (or subtrac-
tion) is performed. If the destination is one of the 16-bit registers, it is first sign extended internally and
concatenated with 16 zero bits to form a 36-bit operand before the operation to the fractional product;
the high-order 16 bits of the result are then stored.
This instruction is used for multiplication and accumulation of fractional data or integer data when a
full 32-bit product is required (see Section 3.3.5.2, “Integer Multiplication,” on page 3-20). When the
destination is a 16-bit register, this instruction is useful only for fractional data.
MAC
Prior to execution, the 16-bit X0 register contains the value $4000, the 16-bit Y1 register contains the
value $0AA0, and the 36-bit A accumulator contains the value $0:0003:0003. Execution of the
MAC X0,Y1,A instruction multiplies the 16-bit signed value in the X0 register by the 16-bit signed
value in Y1, adds the resulting 32-bit product to the 36-bit A accumulator, and stores the result
($0:0553:0003) into the A accumulator. In parallel, X0 and Y1 are updated with new values fetched
from data memory, and the two address registers (R1 and R3) are post-incremented by one.
See Section 3.6.5, “16-Bit Destinations,” on page 3-35 for cases with X0, Y0, or Y1 as D.
See Section 3.6.2, “36-Bit Destinations — CC Bit Set,” on page 3-34 and Section 3.6.4, “20-Bit Des-
tinations — CC Bit Set,” on page 3-34 for the case when the CC bit is set.
LF
15
0003
14
A1
*
SZ — Set according to the standard definition of the SZ bit (parallel move)
L
E
U
N
Z
V
13
*
X0
Y1
— Set if limiting (parallel move) or overflow has occurred in result
— Set if the extension portion of accumulator result is in use
— Set according to the standard definition of the U bit
— Set if MSB of result is set
— Set if result equals zero
— Set if overflow has occurred in result
X0,Y1,A
12
*
MR
11
*
0AA0
Multiply-Accumulate
0003
4000
A0
DSP56800 Family Manual
10
*
I1
9
Assembler Syntax:
MAC
MAC
MAC
X:(R1)+,Y1
I0
8
SZ
7
After Execution
L
6
A2
0
E
5
(+)S1,S2,D
S1,S2,D
S1,S2,D
X:(R3)+,X0
U
4
CCR
0553
A1
N
3
X0
Y1
Z
2
V
(single parallel move)
(dual parallel read)
1
Freescale Semiconductor
0003
2000
0450
C
0
A0
MAC