dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 48

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Data Arithmetic Logic Unit
3.1.1
The data ALU registers (X0, Y1, and Y0) are 16-bit registers that serve as inputs for the data ALU. Each
register may be read or written by the CGDB as a word operand. They may be treated as three independent
16-bit registers, or as one 16-bit register and one 32-bit register. Y1 and Y0 can be concatenated to form
the 32-bit register Y, with Y1 being the most significant word and Y0 being the least significant word.
Figure 3-2 shows this arrangement.
These data ALU input registers are used as source operands for most data ALU operations and allow new
operands to be loaded from the memory for the next instruction while the register contents are used by the
current instruction. X0 may also be written by the XDB2 during the dual read instruction. Certain
arithmetic operations also allow these registers to be specified as destinations.
3.1.2
The two 36-bit data ALU accumulator registers can be accessed either as a 36-bit register (A or B) or as the
following, individual portions of the register:
The three individual portions make up the entire accumulator register, as shown in Figure 3-2.
These two techniques for accessing the accumulator registers provide important flexibility for both DSC
algorithms and general-purpose computing tasks. Accessing these registers as entire accumulators (A or B)
is particularly useful for DSC tasks, because this preserves the full precision of multiplication and other
ALU operations. Data limiting and saturation are also possible using the full registers, in cases where the
final result of a computation that has overflowed is moved (see Section 3.4.1, “Data Limiter,” on page
3-26).
3-4
•
•
•
4-bit extension register (A2 or B2)
16-bit MSP (A1 or B1)
16-bit LSP (A0 or B0)
Data ALU Input Registers (X0, Y1, and Y0)
Data ALU Accumulator Registers
15
X0
A
B
35
35
Figure 3-2. Data ALU Programming Model
3
3
A2
B2
0
32
32
0
0
31
15
31
15
Data Arithmetic Logic Unit
DSP56800 Family Manual
Data ALU Input Registers
Accumulator Registers
Y
A1
B1
15
31
16 15
16 15
0 15
0 15
Y1
16 15
A0
B0
0
15
0
0
0
0
Y0
Freescale Semiconductor
0
0
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