dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 26

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Introduction
and the use of local variables. The veteran DSC programmer sees a powerful DSC instruction set with
many different arithmetic operations and flexible single- and dual-memory moves that can occur in parallel
with an arithmetic operation. The general-purpose nature of the instruction set also allows for an efficient
compiler implementation.
A variety of standard peripherals can be added around the DSP56800 core (see Figure 1-1 on page 1-1)
such as serial ports, general-purpose timers, real-time and watchdog timers, different memory
configurations (RAM, FLASH, or both), and general-purpose I/O (GPIO) ports.
On-Chip Emulation (OnCE™) capability is provided through a debug port conforming to the Joint Test
Action Group (JTAG) standard. This provides real-time, embedded system debugging with on-chip
emulation capability through the five-pin JTAG interface. A user can set hardware and software
breakpoints, display and change registers and memory locations, and single step or step through multiple
instructions in an application.
The DSP56800’s efficient instruction set, multiple internal buses, on-chip program and data memories,
external bus interface, standard peripherals, and industry-standard debug support make the DSP56800
Family an excellent solution for real-time embedded control tasks. It is an excellent fit for wireless or
wireline DSC applications, digital control, and controller applications in need of more processing power.
1.1.1
The DSP56800 core is a programmable 16-bit CMOS digital signal controller that consists of a 16-bit data
arithmetic logic unit (ALU), a 16-bit address generation unit (AGU), a program decoder, On-Chip
Emulation (OnCE), associated buses, and an instruction set. Figure 1-2 on page 1-3 shows a block diagram
of the DSP56800 core. The main features of the DSP56800 core include the following:
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Processing capability of up to 35 million instructions per second (MIPS) at 70 MHz
Requires only 2.7–3.6 V of power
Single-instruction cycle 16-bit x 16-bit parallel multiply-accumulator
Two 36-bit accumulators including extension bits
Single-instruction 16-bit barrel shifter
Parallel instruction set with unique DSC addressing modes
Hardware DO and REP loops
Two external interrupt request pins
Four 16-bit internal core data buses
Three 16-bit internal address buses
Instruction set that supports both DSC and controller functions
Controller-style addressing modes and instructions for smaller code size
Efficient C compiler and local variable support
Software subroutine and interrupt stack with unlimited depth
On-Chip Emulation for unobtrusive, processor-speed-independent debugging
Low-power wait and stop modes
Operating frequency down to DC
Single power supply
Core Overview
DSP56800 Family Manual
Freescale Semiconductor