dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 265

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

AND
Operation:
S•D → D
S•D[31:16] → D[31:16]
where • denotes the logical AND operator
Description: Perform a logical AND operation on the source operand (S) and the destination operand (D), and store
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Instruction Fields:
Timing:
Memory:
Freescale Semiconductor
Operation
AND
Before Execution
A2
X0
6
the result in the destination. This instruction is a 16-bit operation. If the destination is a 36-bit accumu-
lator, the operation is performed on the source and bits 31–16 of the accumulator. The remaining bits
of the destination accumulator are not affected. The result is not affected by the saturation bit (SA).
This instruction is used for the logical AND of two registers; the ANDC instruction is appropriate to
AND a 16-bit immediate value with a register or memory location.
AND
Prior to execution, the 16-bit X0 register contains the value $7F00, and the 36-bit A accumulator con-
tains the value $6:1234:5678. The AND X0,A instruction logically ANDs the 16-bit value in the X0
register with bits 31–16 of the A accumulator (A1) and stores the 36-bit result in the A accumulator.
Bits 35–32 in the A2 register and bits 15–0 in the A0 register are not affected by this instruction.
See Section 3.6.5, “16-Bit Destinations,” on page 3-35 for cases with X0, Y0, or Y1 as D.
See Section 3.6.2, “36-Bit Destinations — CC Bit Set,” on page 3-34 and Section 3.6.4, “20-Bit Des-
tinations — CC Bit Set,” on page 3-34 for the case when the CC bit is set.
2 oscillator clock cycles
1 program word
LF
15
1234
7F00
14
A1
*
N
Z
V
13
*
Operands
— Set if bit 31 of accumulator result or MSB of register result is set
— Set if bits 31–16 of accumulator result or all bits or register result are zero
— Always cleared
DD,FDD
F1,DD
X0,A
12
*
MR
11
*
5678
A0
10
*
Instruction Set Details
Logical AND
I1
9
C
2
Assembler Syntax:
AND
AND
; AND X0 with A1
I0
8
W
1
SZ
7
After Execution
16-bit logical AND
6
L
A2
X0
6
5
E
S,D
S,D
U
4
CCR
7F00
1200
A1
N
3
Z
Comments
2
V
1
5678
C
0
A0
AND
A-35