dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 240

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

For the ASLL instruction, if the CC bit is set, the N bit is always cleared. If CC is 0, the N bit is set
according to the standard definition outlined in the preceding discussion.
A.4.1.6
The Z bit is updated based on the result of a data ALU operation. Z is set if the result of an operation is zero
— that is, all significant bits are set to zero. It is cleared otherwise.
The number of bits used to compute the value for Z is determined by the size of the result and whether or
not the OMR’s CC bit is set:
For 36-bit results:
For 32-bit results:
For 20-bit results:
For 16-bit results:
Z is not affected by the OMR’s SA bit.
A.4.1.7
The V bit is updated under the following conditions. If the SA bit in the OMR is set to one, V is set when
saturation occurs in the MAC Output Limiter. If the SA bit is zero or no saturation occurs, it is set when an
arithmetic overflow occurs as the result of a data ALU operation. Overflow occurs when the carry into the
result’s MSB is not equal to the carry out of the MSB, thus changing the sign of the value. The result of the
ALU operation is therefore not representable in the destination — the result has overflowed. V is cleared
when overflow does not occur.
In general, overflow is calculated based on the size of the result or destination of the operation. When the
CC bit in the OMR is set, however, overflow is determined based on the 32-bit result for what would
otherwise be 36-bit results. The same is true for 20-bit results: when the CC bit is set, overflow is
determined based on the 16-bit result.
For the IMPY instruction, V is set if the computed result does not fit in 16 bits and is cleared otherwise.
The SA bit has no effect in this case.
A.4.1.8
The C bit is updated based on the result of a data ALU operation. C is set either if a carry is generated out
of the most significant bit (MSB) of the result for an addition, or if a borrow is generated in a subtraction.
C is cleared otherwise.
For 20- or 36-bit results, the carry or borrow is generated out of bit 35. For 32-bit results, the carry or
borrow is generated out of bit 31. The carry or borrow is generated out of bit 15 for 16-bit results.
C is not affected by the OMR’s CC or SA bits.
A-10
Z is set if bits 35 to 0 of the result are all zero, or bits 31 to 0 if the OMR’s CC bit is set.
Z is set if bits 31 to 0 of the result are all zero. It is set using bits 15 to 0 of the result if Y1, Y0, or
X0 is the destination.
Z is set if bits 35 to 16 of the result are all zero, or bits 31 to 16 if the OMR’s CC bit is set.
Z is set if bits 31 to 16 of the result are all zero for A, B, Y; it is set if bits 15 to 0 of the result are
all zero for 16-bit destinations.
Zero (Z) — Bit 2
Overflow (V) — Bit 1
Carry (C) — Bit 0
DSP56800 Family Manual
Freescale Semiconductor