dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 252

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Three examples using the preceding tables follow.
A-22
Problem
Calculate the number of DSP56800 instruction program words and the number of oscillator clock cycles
required for the following instruction:
Where the following conditions are true:
Solution
To determine the number of instruction program words and the number of oscillator clock cycles required
for the given instruction, the user should perform the following steps:
•
•
•
•
1. Look up the number of instruction program words and the number of oscillator clock cycles
X:
X:
P:
P:
IO:
X:X:
X:X:
X:X:
Access
Type
MACR
Operating mode register (OMR) = $02 (normal expanded memory map).
External X memory accesses require zero wait state, (assume external mem requires no wait state
and BCR contains the value $00).
R0 address register = $C000 (external X memory).
R3 address register = $0052 (internal X memory).
required for the opcode-operand portion of the instruction inTable A-11 on page A-18.
According to Table A-11 on page A-18, the MACR instruction will require one instruction
program word and will execute in (2 + mv) oscillator clock cycles. The term “mv”
represents the additional instruction program words (if any) and the additional oscillator
clock cycles (if any) that may be required over and above those needed for the basic MACR
instruction due to the parallel move portion of the instruction.
1.
2.
wx — external X memory access wait states
wp — external P memory access wait states
Int
Ext
Int:Int
Ext:Int
I/O:Int
—
—
—
X0,Y0,A
X Memory
Example A-1. Arithmetic Instruction with Two Parallel Reads
Access
Table A-20. Memory Access Timing Summary
X:(R0)+,Y0
P Memory
Access
Ext
Int
—
—
—
—
—
—
DSP56800 Family Manual
X:(R3)+,X0
I/O Access
Int
—
—
—
—
—
—
—
Access
+ ax
wx
—
—
—
—
—
—
0
1
Cycle
+ ap
wp
—
—
—
—
—
—
0
2
Freescale Semiconductor
Cycle
+ aio
—
—
—
—
—
—
—
0
+ axx
Cycle
wx
—
—
—
—
—
0
0