dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 339

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

MOVE(C)
Operation:
X:<ea>→ D
S → X:<ea>
S → D
Description: Move the contents of the specified source (control) register (S) to the specified destination, or move
Note:
Note:
Freescale Semiconductor
the specified source to the specified destination (control) register (D). The control registers S and D
consist of the AGU registers, data ALU registers, and the program controller registers. These registers
may be moved to or from any other register or location in X data memory.
If the HWS is specified as a destination operand, the contents of the first HWS location are copied into
the second one, and the LF and NL bits are updated accordingly. If the HWS is specified as a source
operand, the contents of the second HWS location are copied into the first one, and the LF and NL bits
are updated accordingly. This allows more efficient manipulation of the HWS.
When a 36-bit accumulator (A or B) is specified as a source operand, there is a possibility that the data
may be limited. If the data out of the shifter indicates that the accumulator extension register is in use,
and the data is to be moved into a 16-bit destination, the value stored in the destination is limited to a
maximum positive or negative saturation constant to minimize truncation error. Limiting does not oc-
cur if an individual 16-bit accumulator register (A1, A0, B1, or B0) is specified as a source operand
instead of the full 36-bit accumulator (A or B). This limiting feature allows block floating-point oper-
ations to be performed with error detection since the L bit in the CCR is latched (that is, sticky).
When a 36-bit accumulator (A or B) is specified as a destination operand, any 16-bit source data to be
moved into that accumulator is automatically extended to 36 bits by sign extending the MSB of the
source operand (bit 15) and appending the source operand with 16 LS zeros. The automatic sign ex-
tension and zeroing features may be circumvented by specifying the destination register to be one of
the individual 16-bit accumulator registers (A1 or B1).
Due to pipelining, if an address register (Rj, SP, or M01) is changed with a MOVE or bit-field instruc-
tion, the new contents will not be available for use as a pointer until the second following instruction.
If the SP is changed, no PUSH or POP instructions are permitted until the second following instruction.
If the N address register is changed with a MOVE instruction, this register’s contents will be available
for use on the immediately following instruction. In this case the instruction that writes the N address
register will be stretched one additional instruction cycle. This is true for the case when the N register
is used by the immediately following instruction; if N is not used, then the instruction is not stretched
an additional cycle. If the N address register is changed with a bit-field instruction, the new contents
will not be available for use until the second following instruction.
Move Control Register
Instruction Set Details
Assembler Syntax:
MOVEC
MOVEC
MOVEC
X:<ea>,D
S,X:<ea>
S,D
MOVE(C)
A-109