dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 414

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

B.1.7.3
Figure B-5 shows a memory map for this implementation of the double-precision delayed LMS adaptive
filter.
B-18
; Delayed LMS algorithm with matched coefficient and data vectors
; Algorithm runs in 5N (2 coeffs processed in each 10 cycle loop)
; Data Sample is stored in Y0 and Y1.
; Coefficient is stored in X0
; Loop Gain * Error is stored in X:(R2) (will be placed in X0).
; FIR operation done in B.
; Coeff update operation done in A.
; FIR sum = a
; c(k)
opt
PUSH
MOVE
MOVE
MOVE
MOVE
MOVE
CLR
MOVE
DO
MAC
MOVE
TFR
MOVE
MACR
MAC
MOVE
new
Double Precision Delayed
= b = c(k)
cc
M01
#X_Vec7,R0
#NTaps,M01
#Coeff,R3
#Coeff-2,R1
#0,N
B
#NTaps/2,EndDO1_7_3
Y0,X0,B
X0,A
X0,Y1,A
X0,Y1,B
Figure B-5. LMS Adaptive Filter — Double Precision Delayed Memory Map
= a +c(k)
X:(R0)+,Y0
X:(R0)+,Y1
A,X:(R1)+
A0,X:(R1)+
X:(R2)+N,X0
X:(R0)+,Y0
A,X:(R1)+
A0,X:(R1)+
old
old
-mu*e
r1, r3
*x(n-k)
r0
old
DSP56800 Family Manual
X:(R3)+,X0 ; 1
X:(R3)+,A0 ; 1
X:(R3)+,X0 ; 1
*x(n-k-1)
X memory
x(n-N+1)
x(n-1)
c0_H
c1_H
c0_L
c1_L
x(n)
.
; 2
; 2
; 2
; 2
; 2
; 1
; 1
; 2
; 1
; 1
; 1
; 1
; 1
2
2
2
2
2
1
1
1
3
1
1
1
1
1
1
1
save addr mode state
start of X
modulo NTaps
start of coefficients
start of delayed coef
to emulate (Rn) adr mode
y0 = x[n]
y1= x[n-1], x0=c[0,H]
do FIR and update coefficients
update coefficient
update coefficient
x0=loop gain * error
a0=c[k,L]
x0=c[k+1,H]
update coefficient
update coefficient
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AA0083