dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 172

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Interrupts and the Processing States
It is required that a two-word JSR instruction is present in any interrupt vector location that may be fetched
during exception processing. If an interrupt vector location is unused, then the JSR instruction is not
required.
The hardware reset and COP reset are special cases because they are reset vectors, not interrupt vectors.
There is no IPL specified for these two because these conditions reset the chip and reset takes precedence
over any interrupt. Typically a two-word JMP instruction is used in the reset vectors. The hardware reset
vector will either be at address $0000 or $E000 and the COP reset vector will either be at $0002 or $E002
depending on the operating mode of the chip. The different operating modes are discussed in
Section 5.1.9.1, “Operating Mode Bits (MB and MA) — Bits 1–0,” on page 5-10.
7.3.3
Interrupts are organized in a simple priority structure. Each interrupt source has an associated IPL: Level 0
or Level 1. Level 0, the lowest level, is maskable, and Level 1 is non-maskable. Table 7-5 summarizes the
priority levels and their associated interrupt sources.
The interrupt mask bits (I1, I0) in the SR reflect the current priority level and indicate the IPL needed for
an interrupt source to interrupt the processor (see Table 7-6). Interrupts are inhibited for all priority levels
below the current processor priority level. Level 1 interrupts, however, are not maskable and, therefore,
can always interrupt the processor.
7.3.4
The interrupt unit in the DSP56800 core supports seven interrupt channels for use by on-chip peripherals,
in addition to the IRQ interrupts and interrupts generated by the DSC core. Each maskable interrupt source
can individually be enabled or disabled as required by the application. The exact method for doing so is
dependent on the particular DSP56800-based device, as some of the interrupt handling logic is
implemented as an on-chip peripheral.
One example of how interrupts can be enabled and disabled, and their priority level established, is with an
interrupt priority register (IPR).
7-8
Interrupt Priority Structure
Configuring Interrupt Sources
I1
0
0
1
1
IPL
0
1
Table 7-6. Interrupt Mask Bit Definition in the Status Register
I0
0
1
0
1
Non-maskable
Table 7-5. Interrupt Priority Level Summary
Description
(Reserved)
IPL 0, 1
(Reserved)
IPL 1
Maskable
Exceptions Permitted
DSP56800 Family Manual
On-chip peripherals,
IRQA and IRQB
Illegal instruction, OnCE trap,
HWS overflow, SWI
Interrupt Sources
(Reserved)
None
(Reserved)
IPL 0
Exceptions Masked
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