dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 178

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Interrupts and the Processing States
two interrupts programmed at the same priority level (non-maskable or level 0), Table 7-7 shows the
exception priorities within the same priority level. The information in this table only applies when two
interrupts arrive simultaneously or where two interrupts are simultaneously pending.
Whenever a level 0 interrupt has been recognized and exception processing begins, the DSP56800
interrupt controller changes the interrupt mask bits in the program controller’s SR to allow only level 1
interrupts to be recognized. This prevents another level 0 interrupt from interrupting the interrupt service
routine in progress. If an application requires that a level 0 interrupt can interrupt the current interrupt
service routine, it is necessary to use one of the techniques discussed in Section 8.10.1, “Setting Interrupt
Priorities in Software,” on page 8-30.
7.3.7
The interrupt controller generates an interrupt instruction fetch address, which points to the second
instruction word of a two-word JSR instruction located in the interrupt vector table. This address is used
instead of the PC for the next instruction fetch. While the interrupt instructions are being fetched, the PC is
loaded with the address of the interrupt service routine contained within the JSR instruction. After the
interrupt vector has been fetched, the PC is used for any subsequent instruction fetches and the interrupt is
guaranteed to be executed.
Upon executing the JSR instruction fetched from the interrupt vector table, the processor enters the
appropriate interrupt service routine and exits the exception processing state. The instructions of the
interrupt service routine are executed in the normal processing state and the routine is terminated with an
RTI instruction. The RTI instruction restores the PC to the program originally interrupted and the SR to its
contents before the interrupt occurred. Then program execution resumes. Figure 7-5 shows the interrupt
service routine. The interrupt service routine must be told to return to the main program by executing an
RTI instruction.
The execution of an interrupt service routine always conforms to the following rules:
7-14
1. A JSR to the starting address of the interrupt service routine is located at the first of two
2. The interrupt mask bits of the SR are updated to mask level 0 interrupts.
3. The first instruction word of the next interrupt service (of higher IPL) will reach the decoder
4. The interrupt service routine can be interrupted (that is, nested interrupts are supported).
5. The interrupt routine, which can be any length, should be terminated by an RTI, which
interrupt vector addresses.
only after the decoding of at least four instructions following the decoding of the first
instruction of the previous interrupt.
restores the PC and SR from the stack.
The Interrupt Pipeline
DSP56800 Family Manual
Freescale Semiconductor