dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 155

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

ALIAS: the ANDC, EORC, ORC, and NOTC can also be used to perform logical operations on registers
and data memory locations. ANDC, EORC, and ORC allow logical operations with 16-bit immediate data.
See Section 6.5.1, “ANDC, EORC, ORC, and NOTC Aliases,” for additional information.
Freescale Semiconductor
Operation
Operation
Operation
NORM
TSTW
TFR
TST
AND
EOR
NOT
OR
Table 6-25. Data ALU Arithmetic Instructions (Continued)
(except HWS)
X:(Rn+xxxx)
Operands
X:(R2+xx)
Table 6-26. Data ALU Miscellaneous Instructions
Operands
X:(Rn+N)
X:(Rn)+N
X:(SP-xx)
(parallel)
(parallel)
DDDDD
X:(Rn)+
X:(Rn)-
X:<<pp
X:xxxx
X:(Rn)
R0,F
DD,F
~F,F
X:aa
Table 6-27. Data ALU Logical Instructions
Operands
F
DD,FDD
DD,FDD
DD,FDD
F1,DD
F1,DD
F1,DD
FDD
Instruction Set Introduction
C
2
C
2
2
2
2
2
2
4
2
6
4
4
2
2
4
W
W
1
1
1
1
1
2
1
1
1
2
1
1
1
1
1
C
2
2
2
2
Transfer register to register.
Transfer one accumulator to another (36-bits).
~F,F refers to any of two valid combinations: A,B or B,A
Refer to Table 6-35 on page 6-29.
Test 36-bit accumulator.
Refer to Table 6-35 on page 6-29.
Test 16-bit word in register. All registers allowed except
HWS. Limiting can occur if an accumulator specified and
the extension register is in use.
Test a word in memory using appropriate addressing mode.
X:aa represents a 6-bit absolute address. Refer to Absolute
Short Address (Direct Addressing): <aa> on page 4-22.
Refer to Table 6-29 for another form of TSTW that tests and
decrements an AGU register; (executed in the AGU unit).
Normalization iteration instruction for normalizing the F
accumulator
W
1
1
1
1
16-bit logical AND
16-bit exclusive OR (XOR)
One’s-complement (bit-wise negation)
16-bit logical OR
DSP56800 Instruction Set Summary
Comments
Comments
Comments
6-23