dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 177

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

interrupts are prioritized according to the IPLs shown in Table 7-7, and the interrupt source with the
highest priority is selected. The interrupt vector corresponding to that source is then placed on the program
address bus so that the program controller can fetch the interrupt instruction.
Interrupts from a given source are not buffered. The processor will not arbitrate a new interrupt from the
same source until after it fetches the second word of the interrupt vector of the current interrupt.
An internal interrupt-acknowledge signal clears the appropriate interrupt-pending flag for DSC core
interrupts. Some peripheral interrupts may also be cleared by the internal interrupt-acknowledge signal, as
defined in their specifications. Peripheral interrupt requests that need a read/write action to some register
do not receive the internal interrupt-acknowledge signal, and their interrupt requests will remain pending
until their registers are read/written. Further, if the interrupt comes from an IRQ pin and is programmed as
level triggered, the interrupt request will not be cleared. The acknowledge signal will be generated after the
interrupt vectors have been generated, not before.
If more than one interrupt is pending when an instruction is executed, the processor will first service the
interrupt with the highest priority level. When multiple interrupt requests with the same IPL are pending, a
second fixed-priority structure within that IPL determines which interrupt the processor will service. For
Freescale Semiconductor
Priority
Highest
Lowest
Higher
Lower
Table 7-7. Fixed Priority Structure Within an IPL
Hardware RESET
Watchdog timer reset
Illegal instruction
HWS overflow
OnCE trap
SWI
IRQA (external interrupt)
IRQB (external interrupt)
Channel 6 peripheral interrupt
Channel 5 peripheral interrupt
Channel 4 peripheral interrupt
Channel 3 peripheral interrupt
Channel 2 peripheral interrupt
Channel 1 peripheral interrupt
Channel 0 peripheral interrupt
Interrupts and the Processing States
Level 1 (Non-maskable)
Level 0 (Maskable)
Exception
Enabled By
IPR bit 10
IPR bit 11
IPR bit 12
IPR bit 13
IPR bit 14
IPR bit 15
IPR bit 1
IPR bit 4
IPR bit 9
—
—
—
—
—
—
Exception Processing State
7-13