dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 169

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Section 4.4, “Pipeline Dependencies,” on page 4-33 contains more details on interlocks caused during
address generation.
7.3
The exception processing state is the state where the DSC core recognizes and processes interrupts that can
be generated by conditions inside the DSC or from external sources. Upon the occurrence of an event,
interrupt processing transfers control from the currently executing program to an interrupt service routine,
with the ability to later return to the current program upon completion of the interrupt service routine. In
digital signal processing, some of the main uses of interrupts are to transfer data between DSC memory
and a peripheral device or to begin execution of a DSC algorithm upon reception of a new sample. An
interrupt can also be used to exit the DSC’s low-power wait processing state.
An interrupt will cause the processor to enter the exception processing state. Upon entering this state, the
current instruction in decode executes normally. The next fetch address is supplied by the interrupt
controller and points into the interrupt vector table (Table 7-4 on page 7-7). During this fetch the PC is not
updated. The instruction located at these two addresses in the interrupt vector table must always be a
two-word, unconditional jump-to-subroutine instruction (JSR). Note that the interrupt controller only
fetches the second word of the JSR instruction. This results in the program changing flow to an interrupt
routine, and a context switch is performed.
There are many sources for interrupts on the DSP56800 Family of chips, and some of these sources can
generate more than one interrupt. Interrupt requests can be generated from conditions within the DSC core,
from the DSC peripherals, or from external pins. The DSC core features a prioritized interrupt vector
scheme with up to 64 vectors to provide faster interrupt servicing. The interrupt priority structure is
discussed in Section 7.3.3, “Interrupt Priority Structure.”
7.3.1
The following steps occur in exception processing:
Freescale Semiconductor
In this case, before the first MOVE instruction has written R2 during its execution cycle, the second MOVE has accessed the old
R2, using the old contents of R2. This is because the address for indirect moves is formed during the decode cycle. This overlap-
ping instruction execution in the pipeline causes the pipeline effect.
After an address register has been written by a MOVE instruction, one instruction cycle should be allowed before the new con-
tents are available for use as an address register by another MOVE instruction. The proper instruction sequence follows:
1. A request for an interrupt is generated either on a pin, from the DSC core, from a peripheral
on the DSC chip, or from an instruction executed by the DSC core. Any hardware interrupt
request from a pin is first synchronized with the DSC clock.
Exception Processing State
MOVE X0,R2
MOVE X:(R2),A
MOVE X0,R2
NOP
MOVE X:(R2),A
Sequence of Events in the Exception Processing State
Example 7-2. Common Pipeline Dependency Code Sequence
; Move a value into register R2
; Uses the OLD contents of R2 to address memory.
; Moves a number into register R2
; Executes any instruction or instruction sequence not
; using the R2 register written in the previous
; instruction
; Uses the new contents of R2
Interrupts and the Processing States
Exception Processing State
7-5