dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 15

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

List of Figures
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 1-6
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-15
Figure 3-16
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Freescale Semiconductor
DSP56800-Based DSC Microcontroller Chip . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
DSP56800 Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Example of Chip Built Around the DSP56800 Core . . . . . . . . . . . . . . . . . . . . . 1-5
Analog Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Mapping DSC Algorithms into Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
DSP56800 Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
DSP56800 Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Sample DSP56800-Family Chip Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 2-7
DSP56800 Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Data ALU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Data ALU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Right and Left Shifts Through the Multi-Bit Shifting Unit . . . . . . . . . . . . . . . . 3-6
Writing the Accumulator Extension Registers (F2) . . . . . . . . . . . . . . . . . . . . . . 3-8
Reading the Accumulator Extension Registers (F2). . . . . . . . . . . . . . . . . . . . . . 3-9
Writing the Accumulator by Portions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Writing the Accumulator as a Whole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Bit Weightings and Operand Alignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Word-Sized Integer Addition Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Comparison of Integer and Fractional Multiplication . . . . . . . . . . . . . . . . . . . 3-19
MPY Operation — Fractional Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Integer Multiplication (IMPY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Single-Precision Times Double-Precision Signed Multiplication . . . . . . . . . . 3-24
Example of Saturation Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Convergent Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
Two’s-Complement Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Address Generation Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Address Generation Unit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Address Register Indirect: No Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Address Register Indirect: Post-Increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Address Register Indirect: Post-Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Address Register Indirect: Post-Update by Offset N . . . . . . . . . . . . . . . . . . . . 4-13
Address Register Indirect: Indexed by Offset N. . . . . . . . . . . . . . . . . . . . . . . . 4-14
Address Register Indirect: Indexed by Short Displacement . . . . . . . . . . . . . . . 4-15
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