dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 365

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

NOTC
Operation:
X:<ea> → X:(ea)
D → D
Implementation Note:
Description: Take the one’s complement of the destination operand (D), and store the result in the destination. This
Example:
Explanation of Example:
Condition Codes Affected:
Freescale Semiconductor
This instruction is an alias to the BFCHG instruction, and assembles as BFCHG with the 16-bit imme-
diate mask set to $FFFF. This instruction will disassemble as a BFCHG instruction.
instruction is a 16-bit operation. If the destination is a 36-bit accumulator, the one’s-complement is
performed on bits 31–16 of the accumulator. The remaining bits of the destination accumulator are not
affected. C is also modified as described in following discussion.
NOTC
Prior to execution, the R2 register contains the value $CAA3. Execution of the instruction comple-
ments the value in R2. C is modified as described in following discussion.
For destination operand SR:
For other destination operands:
Before Execution
15
LF
SR
R2
14
*
?
L
C
13
*
— Changed if specified in the field
— Set if data limiting occurred during 36-bit source move
— Set if the value equals $FFFF before the complement
Logical Complement with Carry
R2
12
CAA3
3456
*
MR
11
*
10
*
Instruction Set Details
I1
9
Assembler Syntax:
NOTC
NOTC
I0
8
SZ
7
L
6
After Execution
5
E
X:<ea>
D
4
U
CCR
SR
R2
3
N
2
Z
355C
3456
1
V
C
0
NOTC
A-135