dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 357

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

MPYSU
Operation:
S1 * S2 → D (S1 signed, S2 unsigned)
Description: Multiply one signed 16-bit source operand by one unsigned 16-bit operand, and place the 32-bit frac-
Usage:
Example:
Explanation of Example:
Condition Codes Affected:
Freescale Semiconductor
Before Execution
A2
0
tional product in the destination (D). The order of the registers is important. The first source register
(S1) must contain the signed value, and the second source (S2) must contain the unsigned value to pro-
duce correct fractional results. If the destination is one of the 16-bit registers, only the high-order
16 bits of the fractional result are stored. The result is not affected by the state of the saturation bit
(SA). Note that for 16-bit destinations, the sign bit may be lost for large fractional magnitudes.
In addition to single-precision multiplication of a signed value times unsigned value, this instruction
is also used for multi-precision multiplications, as shown in Section 3.3.8.2, “Multi-Precision Multi-
plication,” on page 3-23.
MPYSU
The 16-bit X0 register contains the value $3456, and the 16-bit Y0 register contains the value $8000.
Execution of the MPYSU X0,Y0,A instruction multiplies the 16-bit signed value in the X0 register
by the 16-bit unsigned value in Y0 and stores the signed result into the A accumulator. If this was a
MPY instruction, Y0 ($8000) would equal -1.0, and the multiplication result would be
$F:CBAA:0000. Since this is an MPYSU instruction, Y0 is considered unsigned and equals +1.0. This
gives a multiplication result of $0:3456:0000.
See Section 3.6.5, “16-Bit Destinations,” on page 3-35 for cases with X0, Y0, or Y1 as D.
See Section 3.6.2, “36-Bit Destinations — CC Bit Set,” on page 3-34 and Section 3.6.4, “20-Bit Des-
tinations — CC Bit Set,” on page 3-34 for the case when the CC bit is set.
15
LF
0000
14
A1
*
L
E
U
N
Z
V
13
*
X0
Y0
— Set if overflow has occurred in result
— Set if the extension portion of accumulator result is in use
— Set according to the standard definition of the U bit
— Set if MSB of result is set
— Set if result equals zero
— Always cleared
X0,Y0,A
12
*
MR
Signed Unsigned Multiply
11
*
0000
3456
8000
A0
10
*
Instruction Set Details
I1
9
Assembler Syntax:
MPYSU
I0
8
SZ
7
After Execution
L
6
A2
0
E
5
S1,S2,D
U
4
CCR
3456
A1
N
3
X0
Y0
Z
2
V
1
0000
3456
8000
0
C
A0
MPYSU
A-127