dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 76

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dsp56800

Manufacturer Part Number
dsp56800
Description
16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Data Arithmetic Logic Unit
Once the rounding bit has been programmed in the OMR register, there is a delay of one instruction cycle
before the new rounding mode becomes active.
3-32
Case I
Case II
*A0 is always clear; performed during RND, MPYR, MACR
Before Rounding
35
Before Rounding
35
X X . . X X X X X . . . X X X 0 1 0 0 0 1 1 0 X. . . . . . . X X X
X X . . X X X X X . . . X X X 0 1 0 1 1 1 1 0 X . . . . . . X X X
A2
A2
: A0 < 0.5 ($8000), then round down (add nothing)
32 31
32 31
: A0 >= 0.5 ($8000), then round up (add 1 to A1)
A1
A1
16 15
16 15
0
1
Figure 3-16. Two’s-Complement Rounding
A0
A0
DSP56800 Family Manual
0
0
After Rounding
35
After Rounding
35
X X . . X X X X X . . . X X X 0 1 0 0 0 0 0 . . . . . . . . . 0 0 0
X X . . X X X X X . . . X X X 0 1 0 1 0 0 0 . . . . . . . . . 0 0 0
A2
A2
32 31
32 31
A1
A1
16 15
16 15
Freescale Semiconductor
A0*
A0*
AA0050
0
0

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