dsp56800 Freescale Semiconductor, Inc, dsp56800 Datasheet - Page 210

• Manufacturer Part Number: dsp56800
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Software Techniques
; Hardware Nested Looping Example of the Maximum Depth Allowed
;
;
;
InnerLoop:
OuterLoop:
The HWS’s current depth can be determined by the NL and LF bits, as shown in Table 5-5, “Looping
Status,” on page 5-13. From these bits it is possible to determine whether there are no loops currently in
progress, a single loop, or two nested loops.
For nested DO loops, it is required that there be at least three instructions after the POP of the LA and LC
registers and before the label of any outer loop. This requirement shows up in the preceding example as
three NOPs but can be fulfilled by any other instructions.
Further hardware nesting is possible by saving the contents of the HWS and later restoring the stack on
completion, as described in Section 8.13, “Multitasking and the Hardware Stack.”
8.6.4.3
A comparison of the execution overhead and extra code size of software and hardware outer loops shows
that for loop nesting, it is just as efficient to nest in software (see Table 8-1). If a data ALU register or
AGU register is available for use as the loop count, each loop executes one cycle faster than nesting loops
in hardware. If there are no on-chip registers available for the loop counter, then the third technique can be
used that uses one of the first 64 locations of X data memory. This technique executes one cycle slower per
loop than nesting loops in hardware. Each of the software techniques also uses fewer instruction words.
It is recommended that the nesting of hardware DO loops not be used for implementing nested loops.
Instead, it is recommended that all outer loops in a nested looping scheme be implemented using software
looping techniques. Likewise, it is recommended that software looping techniques be used when a loop
contains a JSR and the called routine contains many instructions or contains a hardware DO loop.
8-24
Hardware nested DO loops
Software using data ALU register
Software using AGU register
Software using memory location
DO
PUSH
PUSH
DO
(instructions)
REP
ASL
(instructions)
POP
POP
NOP
NOP
NOP
Comparison of Outer Looping Techniques
#3,OuterLoop
LC
LA
X0,InnerLoop
Y0
A
LA
LC
Loop Technique
Table 8-1 Outer Loop Performance Comparison
DSP56800 Family Manual
; Beginning of outer loop
; Beginning of inner loop
; Skips ASL if y0 = 0
; End of inner loop
; three instructions required after POP
; three instructions required after POP
; three instructions required after POP
; End of outer loop
Number of Icyc to
Set Up Loop
3
1
1
2
Number of Icyc
Each Loop
Additional
Executed
5
4
4
6
Instruction Words
Freescale Semiconductor
Total Number of
7
3
3
4