EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 98

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.3.5 Vector Table Offset Register
2011-02-04 - d0002_Rev1.00
1
When you write to the ICSR, the effect is Unpredictable if you:
• write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
• write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
The VTOR indicates the offset of the vector table base address from memory address 0x00000000.
See the register summary in Table 4.12 (p. 94) for its attributes.
The bit assignments are:
31 30 29
This is the same value as IPSR bits[8:0], see Section 2.1.3.5.2 (p. 10) .
Bits
[25]
[24]
[23]
[22]
[21:18]
[17:12]
[11]
[10:9]
[8:0]
Name
PENDSTCLR
-
Reserved for
Debug use
ISRPENDING
-
VECTPENDING
RETTOBASE
-
VECTACTIVE
Reserved in som e devices
(See note below)
1
Type
WO
-
RO
RO
-
RO
RO
-
RO
Function
SysTick exception clear-pending bit.
Write:
0 = no effect1 = removes the pending state from the SysTick exception.
This bit is WO. On a register read its value is Unknown.
Reserved.
This bit is reserved for Debug use and reads-as-zero when the processor is not in
Debug.
Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending1 = interrupt pending.
Reserved.
Indicates the exception number of the highest priority pending enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority pending enabled
exception.
The value indicated by this field includes the effect of the BASEPRI and
FAULTMASK registers, but not any effect of the PRIMASK register.
Indicates whether there are preempted active exceptions:
0 = there are preempted active exceptions to execute
1 = there are no active exceptions, or the currently-executing exception is the only
active exception.
Reserved.
Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
Note
Subtract 16 from this value to obtain the IRQ number required to index
into the Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-Pending,
or Priority Registers, see Table 2.5 (p. 10) .
TBLOFF
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98
1
of the currently active exception.
7 6
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Reserved
0