EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 133

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

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List of Tables
1.1. Cortex-M3 configuration in EFM32 series .................................................................................................... 5
2.1. Summary of processor mode, execution privilege level, and stack use options .................................................... 6
2.2. Core register set summary ....................................................................................................................... 7
2.3. PSR register combinations ....................................................................................................................... 9
2.4. APSR bit assignments ............................................................................................................................. 9
2.5. IPSR bit assignments ............................................................................................................................ 10
2.6. EPSR bit assignments ........................................................................................................................... 10
2.7. PRIMASK register bit assignments ........................................................................................................... 11
2.8. FAULTMASK register bit assignments ....................................................................................................... 12
2.9. BASEPRI register bit assignments ............................................................................................................ 12
2.10. CONTROL register bit assignments ........................................................................................................ 13
2.11. Memory access behavior ...................................................................................................................... 16
2.12. SRAM memory bit-banding regions ......................................................................................................... 18
2.13. Peripheral memory bit-banding regions .................................................................................................... 18
2.14. C compiler intrinsic functions for exclusive access instructions ..................................................................... 21
2.15. Properties of the different exception types ................................................................................................ 23
2.16. Exception return behavior ..................................................................................................................... 28
2.17. Faults ................................................................................................................................................ 28
2.18. Fault status and fault address registers ................................................................................................... 30
3.1. Cortex-M3 instructions ........................................................................................................................... 33
3.2. CMSIS intrinsic functions to generate some Cortex-M3 instructions ................................................................ 37
3.3. CMSIS intrinsic functions to access the special registers .............................................................................. 37
3.4. Condition code suffixes .......................................................................................................................... 44
3.5. Memory access instructions .................................................................................................................... 45
3.6. Offset ranges ...................................................................................................................................... 48
3.7. Offset ranges ....................................................................................................................................... 51
3.8. Data processing instructions .................................................................................................................... 56
3.9. Multiply and divide instructions ................................................................................................................ 66
3.10. Packing and unpacking instructions ........................................................................................................ 71
3.11. Branch and control instructions .............................................................................................................. 73
3.12. Branch ranges .................................................................................................................................... 74
3.13. Miscellaneous instructions ..................................................................................................................... 79
4.1. Core peripheral register regions ............................................................................................................... 88
4.2. NVIC register summary ......................................................................................................................... 88
4.3. Mapping of interrupts to the interrupt variables ........................................................................................... 89
4.4. ISER bit assignments ............................................................................................................................ 90
4.5. ICER bit assignments ............................................................................................................................ 90
4.6. ISPR bit assignments ............................................................................................................................ 91
4.7. ICPR bit assignments ............................................................................................................................ 91
4.8. IABR bit assignments ............................................................................................................................ 92
4.9. IPR bit assignments .............................................................................................................................. 92
4.10. STIR bit assignments ........................................................................................................................... 93
4.11. CMSIS functions for NVIC control ........................................................................................................... 94
4.12. Summary of the system control block registers ........................................................................................ 94
4.13. ACTLR bit assignments ........................................................................................................................ 95
4.14. CPUID register bit assignments ............................................................................................................ 96
4.15. ICSR bit assignments ........................................................................................................................... 97
4.16. VTOR bit assignments ........................................................................................................................ 99
4.17. AIRCR bit assignments ........................................................................................................................ 99
4.18. Priority grouping ................................................................................................................................ 100
4.19. SCR bit assignments ......................................................................................................................... 100
4.20. CCR bit assignments ........................................................................................................................ 101
4.21. System fault handler priority fields ........................................................................................................ 102
4.22. SHPR1 register bit assignments .......................................................................................................... 103
4.23. SHPR2 register bit assignments .......................................................................................................... 103
4.24. SHPR3 register bit assignments .......................................................................................................... 103
4.25. SHCSR bit assignments ...................................................................................................................... 104
4.26. MMFSR bit assignments ..................................................................................................................... 106
4.27. BFSR bit assignments ........................................................................................................................ 107
4.28. UFSR bit assignments ........................................................................................................................ 108
4.29. HFSR bit assignments ........................................................................................................................ 109
4.30. MMFAR bit assignments ..................................................................................................................... 110
4.31. BFAR bit assignments ........................................................................................................................ 110
4.32. System timer registers summary ........................................................................................................... 111
4.33. SysTick CTRL register bit assignments .................................................................................................. 111
4.34. LOAD register bit assignments ............................................................................................................. 112
4.35. VAL register bit assignments ............................................................................................................... 112
4.36. CALIB register bit assignments ............................................................................................................. 113
4.37. Memory attributes summary ................................................................................................................. 114
4.38. MPU registers summary ...................................................................................................................... 114
4.39. TYPE register bit assignments ............................................................................................................. 115
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2011-02-04 - d0002_Rev1.00
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