EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 90

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.2.3 Interrupt Clear-enable Registers
4.2.4 Interrupt Set-pending Registers
2011-02-04 - d0002_Rev1.00
Table 4.4. ISER bit assignments
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is
not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never
activates the interrupt, regardless of its priority.
The ICER0 and ICER1 registers disable interrupts, and show which interrupts are enabled. See:
• the register summary in Table 4.2 (p. 88) for the register attributes
• Table 4.3 (p. 89) for which interrupts are controlled by each register.
The bit assignments are:
Table 4.5. ICER bit assignments
The ISPR0 and ISPR1 registers force interrupts into the pending state, and show which interrupts are
pending. See:
• the register summary in Table 4.2 (p. 88) for the register attributes
• Table 4.3 (p. 89) for which interrupts are controlled by each register.
The bit assignments are:
31
31
Bits
[31:0]
Bits
[31:0]
Name
SETENA
Name
CLRENA
Function
Interrupt set-enable bits.
Write:
0 = no effect1 = enable
interrupt.Read:
0 = interrupt disabled
1 = interrupt enabled.
Function
Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
SETPEND bits
CLRENA bits
...the world's most energy friendly microcontrollers
90
www.energymicro.com
0
0