EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 48

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4.2.3 Restrictions
3.4.2.4 Condition flags
3.4.2.5 Examples
3.4.3 LDR and STR, register offset
2011-02-04 - d0002_Rev1.00
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either
be signed or unsigned. See Section 3.3.5 (p. 42) .
Table 3.6 (p. 48) shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Table 3.6. Offset ranges
For load instructions:
• Rt can be SP or PC for word loads only
• Rt must be different from Rt2 for two-word loads
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When Rt is PC in a word load instruction:
• bit[0] of the loaded value must be 1 for correct execution
• a branch occurs to the address created by changing bit[0] of the loaded value to 0
• if the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
• Rt can be SP for word stores only
• Rt must not be PC
• Rn must not be PC
• Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
These instructions do not change the flags.
Load and Store with register offset.
Instruction type
Word, halfword, signed
halfword, byte, or signed byte
Two words
LDR
LDRNE
STR
STRH
LDRD
STRD
R8, [R10]
R2, [R5, #960]!
R2, [R9,#const#struc]
R3, [R4], #4
R8, R9, [R3, #0x20]
R0, R1, [R8], #-16
Immediate offset
#255 to 4095
multiple of 4 in the
range #1020 to 1020
; Loads R8 from the address in R10.
; Loads (conditionally) R2 from a word
; 960 bytes above the address in R5, and
; increments R5 by 960.
; const#struc is an expression evaluating
; to a constant in the range 0#4095.
; Store R3 as halfword data into address in
; R4, then increment R4 by 4
; Load R8 from a word 32 bytes above the
; address in R3, and load R9 from a word 36
; bytes above the address in R3
; Store R0 to address in R8, and store R1 to
; a word 4 bytes above the address in R8,
; and then decrement R8 by 16.
Pre-indexed
#255 to 255
multiple of 4 in the
range #1020 to 1020
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48
Post-indexed
#255 to 255
multiple of 4 in the
range #1020 to 1020
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