EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 18

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.2.5 Bit-banding
2011-02-04 - d0002_Rev1.00
• Self-modifying code. If a program contains self-modifying code, use an ISB instruction immediately
• Memory map switching. If the system contains a memory map switching mechanism, use a DSB
• Dynamic exception priority change. When an exception priority has to change when the exception is
• Using a semaphore in multi-master system. If the system contains more than one bus master, for
Memory accesses to Strongly-ordered memory, such as the system control block, do not require the
use of DMB instructions.
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The
bit-band regions occupy the lowest 1MB of the SRAM and peripheral memory regions.
The memory map has two 32MB alias regions that map to two 1MB bit-band regions:
• accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as shown in
• accesses to the 32MB peripheral alias region map to the 1MB peripheral bit-band region, as shown
Table 2.12. SRAM memory bit-banding regions
Table 2.13. Peripheral memory bit-banding regions
Note
The following formula shows how the alias region maps onto the bit-band region:
Address
range
0x20000000-
0x200FFFFF
0x22000000-
0x23FFFFFF
Address
range
0x40000000-
0x400FFFFF
0x42000000-
0x43FFFFFF
after the code modification in the program. This ensures subsequent instruction execution uses the
updated program.
instruction after switching the memory map in the program. This ensures subsequent instruction
execution uses the updated memory map.
pending or active, use DSB instructions after the change. This ensures the change takes effect on
completion of the DSB instruction.
example, if another processor is present in the system, each processor must use a DMB instruction
after any semaphore instructions, to ensure other bus masters see the memory transactions in the
order in which they were executed.
Table 2.12 (p. 18)
in Table 2.13 (p. 18) .
A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the
SRAM or peripheral bit-band region.
Memory region
SRAM bit-band region
SRAM bit-band alias
Memory region
Peripheral bit-band region
Peripheral bit-band alias
Instruction and data accesses
Direct accesses to this memory range behave as SRAM memory accesses, but
this region is also bit addressable through bit-band alias.
Data accesses to this region are remapped to bit band region. A write operation
is performed as read-modify-write. Instruction accesses are not remapped.
Instruction and data accesses
Direct accesses to this memory range behave as peripheral memory
accesses, but this region is also bit addressable through bit-band alias.
Data accesses to this region are remapped to bit band region. A write
operation is performed as read-modify-write. Instruction accesses are not
permitted.
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