EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 21

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.2.8 Programming hints for the synchronization primitives
2011-02-04 - d0002_Rev1.00
• the word instructions LDREX and STREX
• the halfword instructions LDREXH and STREXH
• the byte instructions LDREXB and STREXB.
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform a guaranteed read-modify-write of a memory location, software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Update the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and
Software can use the synchronization primitives to implement a semaphores as follows:
1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address.
3. If the returned status bit from step 2 (p. 21) indicates that the Store-Exclusive succeeded then the
The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor has executed
a Load-Exclusive instruction.
The processor removes its exclusive access tag if:
• It executes a CLREX instruction
• It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
• An exception occurs. This means the processor can resolve semaphore conflicts between different
For more information about the synchronization primitive instructions, see Section 3.4.8 (p. 54) and
Section 3.4.9 (p. 56) .
ANSI C cannot directly generate the exclusive access instructions. Some C compilers provide intrinsic
functions for generation of these instructions:
Table 2.14. C compiler intrinsic functions for exclusive access instructions
The actual exclusive access instruction generated depends on the data type of the pointer passed to
the intrinsic function. For example, the following C code generates the require LDREXB operation:
Instruction
LDREX, LDREXH, or
LDREXB
STREX, STREXH, or
STREXB
CLREX
threads.
tests the returned status bit. If this bit is:
0 The read-modify-write completed successfully,
1 No write was performed. This indicates that the value returned at step 1 (p. 21) might be out
semaphore is free.
software has claimed the semaphore. However, if the Store-Exclusive failed, another process might
have claimed the semaphore after the software performed step 1 (p. 21) .
of date. The software must retry the read-modify-write sequence,
Intrinsic function
unsigned int __ldrex(volatile void *ptr)
int __strex(unsigned int val, volatile
void *ptr)
void __clrex(void)
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