EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 123

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.5.8.3.1 Example of SRD use
4.5.9 MPU design hints and tips
4.5.9.1 MPU configuration for a microcontroller
2011-02-04 - d0002_Rev1.00
bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling
a subregion means another region overlapping the disabled range matches instead. If no other enabled
region overlaps the disabled subregion the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions, With regions of these sizes, you must set
the SRD field to 0x00, otherwise the MPU behavior is Unpredictable.
Two regions with the same base address overlap. Region one is 128KB, and region two is 512KB. To
ensure the attributes from region one apply to the first128KB region, set the SRD field for region two to
b00000011 to disable the first two subregions, as the figure shows.
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the
interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
• except for the RASR, it must use aligned word accesses
• for the RASR it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to
prevent any previous region settings from affecting the new MPU setup.
The EFM32 devices has only a single processor and information on Shareability and cache behavior is
not used. In such a system, program the MPU as follows:
Table 4.48. Memory region attributes for a microcontroller
In the EFM32 devices the shareability and cache policy attributes do not affect the system behavior.
However, using these settings for the MPU regions can make the application code more portable and
also be useful for setups with the DMA Controller. The values given are for typical situations.
Base address of both regions
Memory region
Flash memory
Internal SRAM
External SRAM
Peripherals
TEX
b000
b000
b000
b000
C
1
1
1
0
B
0
0
1
1
S
0
1
1
1
Memory type and attributes
Normal memory, Non-shareable, write-through
Normal memory, Shareable, write-through
Normal memory, Shareable, write-back, write-allocate
Device memory, Shareable
Region 1
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Disabled subregion
Disabled subregion
Region 2, with
subregions
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Offset from
base address
64KB
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