EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 74

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.9.1 B, BL, BX, and BLX
3.9.1.1 Syntax
3.9.1.2 Operation
2011-02-04 - d0002_Rev1.00
Branch instructions.
B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
where:
B
BL
BX
BLX
cond
label is a PC#relative expression. See Section 3.3.6 (p. 42) .
Rm
All these instructions cause a branch to label, or to the address indicated in Rm. In addition:
• The BL and BLX instructions write the address of the next instruction to LR (the link register, R14).
• The BX and BLX instructions cause a UsageFault exception if bit[0] of Rm is 0.
Bcond label is the only conditional instruction that can be either inside or outside an IT block. All
other branch instructions must be conditional inside an IT block, and must be unconditional outside the
IT block, see Section 3.9.3 (p. 76) .
Table 3.12 (p. 74) shows the ranges for the various branch instructions.
Table 3.12. Branch ranges
Mnemonic
BX
CBNZ
CBZ
IT
TBB
TBH
Instruction
B label
Bcond label (outside IT
block)
is branch (immediate).
is branch with link (immediate).
is branch indirect (register).
is branch indirect with link (register).
is an optional condition code, see Section 3.3.7 (p. 43) .
is a register that indicates an address to branch to. Bit[0] of the value in Rm must be 1, but the
address to branch to is created by changing bit[0] to 0.
Brief description
Branch indirect
Compare and Branch if Non Zero
Compare and Branch if Non Zero
If#Then
Table Branch Byte
Table Branch Halfword
Branch range
#16 MB to +16 MB
#1 MB to +1 MB
See
Section 3.9.1 (p. 74)
Section 3.9.2 (p. 75)
Section 3.9.2 (p. 75)
Section 3.9.3 (p. 76)
Section 3.9.4 (p. 78)
Section 3.9.4 (p. 78)
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