EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 117

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.5.4 MPU Region Base Address Register
4.5.4.1 The ADDR field
4.5.5 MPU Region Attribute and Size Register
2011-02-04 - d0002_Rev1.00
The RBAR defines the base address of the MPU region selected by the RNR, and can update the value
of the RNR. See the register summary in Table 4.38 (p. 114) for its attributes.
Write RBAR with the VALID bit set to 1 to change the current region number and update the RNR. The
bit assignments are:
Table 4.42. RBAR bit assignments
The ADDR field is bits[31:N] of the RBAR. The region size, as specified by the SIZE field in the RASR,
defines the value of N:
If the region size is configured to 4GB, in the RASR, there is no valid ADDR field. In this case, the region
occupies the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64KB region must be aligned on
a multiple of 64KB, for example, at 0x00010000 or 0x00020000.
The RASR defines the region size and memory attributes of the MPU region specified by the RNR,
and enables that region and any subregions. See the register summary in Table 4.38 (p. 114) for
its attributes.
If the region size is 32B, the ADDR field is bits [ 31:5] and there is no Reserved field
31
Bits
[31:N]
[(N-1):5]
[4]
[3:0]
N = Log
Name
ADDR
-
VALID
REGION
2
(Region size in bytes),
Function
Region base address field. The value of N depends on the region size. For more information see
Section 4.5.4.1 (p. 117) .
Reserved.
MPU Region Number valid bit:
Write:
0 = RNR not changed, and the processor:
• updates the base address for the region specified in the RNR
• ignores the value of the REGION field
1 = the processor:
• updates the value of the RNR to the value of the REGION field
• updates the base address for the region specified in the REGION field.
Always reads as zero.
MPU region field:
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the RNR.
ADDR
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117
N N-1
Reserved
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5 4 3
REGION
VALID
0