EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 9

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.1.3.5.1 Application Program Status Register
2011-02-04 - d0002_Rev1.00
Access these registers individually or as a combination of any two or all three registers, using the register
name as an argument to the MSR or MRS instructions. For example:
• read all of the registers using PSR with the MRS instruction
• write to the APSR using APSR with the MSR instruction.
The PSR combinations and attributes are:
Table 2.3. PSR register combinations
1
2
See the instruction descriptions Section 3.10.6 (p. 83) and Section 3.10.7 (p. 83) for more
information about how to access the program status registers.
The APSR contains the current state of the condition flags from previous instruction executions. See the
register summary in Table 2.2 (p. 7) for its attributes. The bit assignments are:
Table 2.4. APSR bit assignments
31 30 29 28 27 26 25 24 23
The processor ignores writes to the IPSR bits.
Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
Register
PSR
IEPSR
IAPSR
EAPSR
Bits
[31]
[30]
[29]
[28]
[27]
[26:0]
N
Z C V Q ICI/IT T
Name
N
Z
C
V
Q
-
Type
RW
RO
RW
RW
1, 2
1
2
Function
Negative or less than flag:
0 = operation result was positive, zero, greater than, or equal1 = operation result was negative or
less than.
Zero flag:
0 = operation result was not zero1 = operation result was zero.
Carry or borrow flag:
0 = add operation did not result in a carry bit or subtract operation resulted in a borrow bit1 = add
operation resulted in a carry bit or subtract operation did not result in a borrow bit.
Overflow flag:
0 = operation did not result in an overflow1 = operation resulted in an overflow.
Sticky saturation flag:
0 = indicates that saturation has not occurred since reset or since the bit was last cleared to zero1
= indicates when an SSAT or USAT instruction results in saturation.
This bit is cleared to zero by software using an MRS instruction.
Reserved.
Combination
APSR, EPSR, and IPSR
EPSR and IPSR
APSR and IPSR
APSR and EPSR
Reserved
16 15
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9
Reserved
ICI/IT
10 9 8
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ISR_NUMBER
0