EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 68

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.6.1.5 Examples
3.6.2 UMULL, UMLAL, SMULL, and SMLAL
3.6.2.1 Syntax
3.6.2.2 Operation
3.6.2.3 Restrictions
3.6.2.4 Condition flags
2011-02-04 - d0002_Rev1.00
Signed and Unsigned Long Multiply, with optional Accumulate, using 32#bit operands and producing
a 64#bit result.
op{cond} RdLo, RdHi, Rn, Rm
where:
op
cond
RdHi, RdLo
Rn, Rm
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these
integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits
of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these
integers, adds the 64#bit result to the 64#bit unsigned integer contained in RdHi and RdLo, and writes
the result back to RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It
multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most
significant 32 bits of the result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It
multiplies these integers, adds the 64#bit result to the 64#bit signed integer contained in RdHi and RdLo,
and writes the result back to RdHi and RdLo.
In these instructions:
• do not use SP and do not use PC
• RdHi and RdLo must be different registers.
These instructions do not affect the condition code flags.
MUL
MLA
MULS
MULLT
MLS
R10, R2, R5
R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5
R0, R2, R2
R2, R3, R2
R4, R5, R6, R7
; Multiply, R10 = R2 x R5
; Multiply with flag update, R0 = R2 x R2
; Conditionally multiply, R2 = R3 x R2
; Multiply with subtract, R4 = R7 - (R5 x R6)
is one of:
UMULL Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL Signed Long Multiply.
SMLAL Signed Long Multiply, with Accumulate.
is an optional condition code, see Section 3.3.7 (p. 43) .
are the destination registers. For UMLAL and SMLAL they also hold
the accumulating value.
are registers holding the operands.
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