EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 67

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.6.1 MUL, MLA, and MLS
3.6.1.1 Syntax
3.6.1.2 Operation
3.6.1.3 Restrictions
3.6.1.4 Condition flags
2011-02-04 - d0002_Rev1.00
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32#bit operands, and producing a
32-bit result.
MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra
MLS{cond} Rd, Rn, Rm, Ra
where:
cond
S
Rd
Rn, Rm are registers holding the values to be multiplied.
Ra
The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the
result in Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least
significant 32 bits of the result in Rd.
The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value from Ra,
and places the least significant 32 bits of the result in Rd.
The results of these instructions do not depend on whether the operands are signed or unsigned.
In these instructions, do not use SP and do not use PC.
If you use the S suffix with the MUL instruction:
• Rd, Rn, and Rm must all be in the range R0 to R7
• Rd must be the same as Rm
• you must not use the cond suffix.
If S is specified, the MUL instruction:
• updates the N and Z flags according to the result
• does not affect the C and V flags.
Mnemonic
UMULL
is an optional condition code, see Section 3.3.7 (p. 43) .
is an optional suffix. If S is specified, the condition code flags are updated on the result of the
operation, see Section 3.3.7 (p. 43) .
is the destination register. If Rd is omitted, the destination register is Rn.
is a register holding the value to be added or subtracted from.
Brief description
Unsigned Multiply (32x32), 64-bit result
; Multiply with accumulate
; Multiply with subtract
See
Section 3.6.2 (p. 68)
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