EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 126

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Implementation-specific
Index register
Instruction cycle count
Interrupt handler
Interrupt vector
Little-endian (LE)
Little-endian memory
Load/store architecture
Memory Protection Unit
(MPU)
Prefetching
Read
Region
Reserved
Should Be One (SBO)
2011-02-04 - d0002_Rev1.00
The behavior is not architecturally defined, and does not have to be
documented by individual implementations. Used when there are a number
of implementation options available and the option chosen does not affect
software compatibility.
In some load and store instruction descriptions, the value of this register
is used as an offset to be added to or subtracted from the base register
value to form the address that is sent to memory. Some addressing modes
optionally enable the index register value to be shifted prior to the addition
or subtraction.
See Also Base register.
The number of cycles that an instruction occupies the Execute stage of the
pipeline.
A program that control of the processor is passed to when an interrupt occurs.
One of a number of fixed addresses in low memory, or in high memory if high
vectors are configured, that contains the first instruction of the corresponding
interrupt handler.
Byte ordering scheme in which bytes of increasing significance in a data word
are stored at increasing addresses in memory.
See Also Big-endian, Byte-invariant, Endianness.
Memory in which:
• a byte or halfword at a word-aligned address is the least significant byte
• a byte at a halfword-aligned address is the least significant byte within the
See Also Big-endian memory.
A processor architecture where data-processing operations only operate on
register contents, not directly on memory contents.
Hardware that controls access permissions to blocks of memory. An MPU
does not perform any address translation.
In pipelined processors, the process of fetching instructions from memory to
fill up the pipeline before the preceding instructions have finished executing.
Prefetching an instruction does not mean that the instruction has to be
executed.
Reads are defined as memory operations that have the semantics of a
load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB,
LDRB, and POP.
A partition of memory space.
A field in a control register or instruction format is reserved if the field is to
be defined by the implementation, or produces Unpredictable results if the
contents of the field are not zero. These fields are reserved for use in future
extensions of the architecture or are implementation#specific. All reserved
bits not used by the implementation must be written as 0 and read as 0.
Write as 1, or all 1s for bit fields, by software. Writing as 0 produces
Unpredictable results.
or halfword within the word at that address
halfword at that address.
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