EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 71

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.8 Bitfield instructions
3.8.1 BFC and BFI
3.8.1.1 Syntax
3.8.1.2 Operation
3.8.1.3 Restrictions
3.8.1.4 Condition flags
2011-02-04 - d0002_Rev1.00
Table 3.10 (p. 71) shows the instructions that operate on adjacent sets of bits in registers or bitfields:
Table 3.10. Packing and unpacking instructions
Bit Field Clear and Bit Field Insert.
BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
where:
cond
Rd
Rn
lsb
width is the width of the bitfield and must be in the range 1 to 32#lsb.
BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb. Other
bits in Rd are unchanged.
BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the
low bit position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.
Do not use SP and do not use PC.
These instructions do not affect the flags.
Mnemonic
BFC
BFI
SBFX
SXTB
SXTH
UBFX
UXTB
UXTH
USATNE
is an optional condition code, see Section 3.3.7 (p. 43) .
is the destination register.
is the source register.
is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31.
Brief description
Bit Field Clear
Bit Field Insert
Signed Bit Field Extract
Sign extend a byte
Sign extend a halfword
Unsigned Bit Field Extract
Zero extend a byte
Zero extend a halfword
R0, #7, R5
See
Section 3.8.1 (p. 71)
Section 3.8.1 (p. 71)
Section 3.8.2 (p. 72)
Section 3.8.3 (p. 72)
Section 3.8.3 (p. 72)
Section 3.8.2 (p. 72)
Section 3.8.3 (p. 72)
Section 3.8.3 (p. 72)
; saturate it as a signed 16-bit value and
; write it back to R7
; Conditionally saturate value in R5 as an
; unsigned 7 bit value and write it to R0
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