EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 81

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.10.2.2 Operation
3.10.2.3 Restrictions
3.10.2.4 Condition flags
3.10.2.5 Examples
3.10.3 DMB
3.10.3.1 Syntax
3.10.3.2 Operation
3.10.3.3 Condition flags
2011-02-04 - d0002_Rev1.00
CPSeffect iflags
where:
effect is one of:
iflags is a sequence of one or more flags:
CPS changes the PRIMASK and FAULTMASK special register values. See Section 2.1.3.6 (p. 11) for
more information about these registers.
The restrictions are:
• use CPS only from privileged software, it has no effect if used in unprivileged software
• CPS cannot be conditional and so must not be used inside an IT block.
This instruction does not change the condition flags.
Data Memory Barrier.
DMB{cond}
where:
cond is an optional condition code, see Section 3.3.7 (p. 43) .
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program
order, before the DMB instruction are completed before any explicit memory accesses that appear, in
program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions
that do not access memory.
This instruction does not change the flags.
CPSID i
CPSID f
CPSIE i
CPSIE f
IE Clears the special purpose register.
ID Sets the special purpose register.
i Set or clear PRIMASK.
f Set or clear FAULTMASK.
; Disable interrupts and configurable fault handlers (set PRIMASK)
; Disable interrupts and all fault handlers (set FAULTMASK)
; Enable interrupts and configurable fault handlers (clear PRIMASK)
; Enable interrupts and fault handlers (clear FAULTMASK)
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