EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 114

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.5.1 MPU Type Register
2011-02-04 - d0002_Rev1.00
The Cortex-M3 MPU memory map is unified. This means instruction accesses and data accesses have
same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a
memory management fault. This causes a fault exception, and might cause termination of the process
in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically
based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection.
Configuration of MPU regions is based on memory types, see Section 2.2.1 (p. 15) .
Table 4.37 (p. 114) shows the possible MPU region attributes. Please not that the Shareability
and cache behavior attributes are usually not relevant for the EFM32 devices since these are not
used by other bus masters. However, these can be useful together with the DMA Controller. See
Section 4.5.9.1 (p. 123) for guidelines on using these attributes.
Table 4.37. Memory attributes summary
Use the MPU registers to define the MPU regions and their attributes. The MPU registers are:
Table 4.38. MPU registers summary
The TYPE register indicates how many regions the MPU supports. See the register summary in
Table 4.38 (p. 114) for its attributes. The bit assignments are:
Memory
type
Strongly-
ordered
Device
Normal
Address
0xE000ED90 TYPE
0xE000ED94 CTRL
0xE000ED98 RNR
0xE000ED9C RBAR
0xE000EDA0 RASR
0xE000EDA4 RBAR_A1
0xE000EDA8 RASR_A1
0xE000EDAC RBAR_A2
0xE000EDB0 RASR_A2
0xE000EDB4 RBAR_A3
0xE000EDB8 RASR_A3
Shareability
-
Shared
Non-shared
Shared
Non-shared
Name
Type
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Other attributes
-
-
-
Non-cacheable Write-
through Cacheable Write-
back Cacheable
Non-cacheable Write-
through Cacheable Write-
back Cacheable
Required
privilege
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Reset value Description
0x00000800 Section 4.5.1 (p. 114)
0x00000000 Section 4.5.2 (p. 115)
0x00000000 Section 4.5.3 (p. 116)
0x00000000 Section 4.5.4 (p. 117)
0x00000000 Section 4.5.5 (p. 117)
0x00000000 Alias of RBAR, see Section 4.5.4 (p. 117)
0x00000000 Alias of RASR, see Section 4.5.5 (p. 117)
0x00000000 Alias of RBAR, see Section 4.5.4 (p. 117)
0x00000000 Alias of RASR, see Section 4.5.5 (p. 117)
0x00000000 Alias of RBAR, see Section 4.5.4 (p. 117)
0x00000000 Alias of RASR, see Section 4.5.5 (p. 117)
Description
All accesses to Strongly-ordered memory occur in program
order. All Strongly-ordered regions are assumed to be shared.
Memory-mapped peripherals that several processors share.
Memory-mapped peripherals that only a single processor uses.
Normal memory that is shared between several processors.
Normal memory that only a single processor uses.
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